Clock signal distribution circuit

• US 6,696,863 B2
• Filed: 09/17/2002
• Issued: 02/24/2004
• Est. Priority Date: 09/18/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Yamamoto, Kenji, Nakajima, Kazuhiro
• Primary Examiner(s): Cho, James H
• Application Number:
  US10/244,507
• Publication Number:
  US 20030052724A1
• Time in Patent Office: 525 Days
• Field of Search: 326/93, 326/95, 326/96, 326/101, 327/291, 327/293, 327/295-297
• US Class Current: 326/93
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A tree wiring distributes an externally supplied clock signal to a plurality of first clock buffers. Routes of the tree wiring are designed so that the externally supplied clock signal can reach the plurality of first clock buffer substantially at the same time. The plurality of first clock buffers are connected to all intersections existing on a mesh wiring in one to one correspondence. The plurality of first clock buffers supply a clock signal supplied thereto through the tree wiring, to the mesh wiring. The mesh wiring protrudes from the intersections thereof which face toward outside by a predetermined length in order to keep load imposed on the plurality of first clock buffers uniform. A plurality of second clock buffers are connected to the mesh wiring, and supply clock signals supplied thereto from the plurality of first clock buffers through the mesh wiring, to a plurality of circuit elements.

Claims

1. A clock signal distribution circuit which distributes an externally supplied clock signal to a plurality of circuits, said clock signal distribution circuit comprising:

a tree wiring having wiring routes branched like a tree;

a mesh wiring having meshed wiring routes;

a plurality of first clock buffers which are connected to terminals of said tree wiring, and supply a clock signal supplied thereto from outside through said tree wiring, to said mesh wiring; and

a plurality of second clock buffers which are connected to said mesh wiring, and supply the clock signal supplied thereto from said plurality of first clock buffers through said mesh wiring, to the plurality of circuits,

wherein said plurality of first clock buffers are connected to intersections which exist on the wiring routes of said mesh wiring in one to one correspondence.

2. The clock signal distribution circuit according to claim 1, wherein said mesh wiring protrudes from intersections thereof which face toward outside by a predetermined length, so that load to be imposed on said plurality of first clock buffers becomes uniform.

3. The clock signal distribution circuit according to claim 2, wherein:

said mesh wiring is constituted by a plurality of horizontal wirings arranged in parallel with one another at predetermined intervals, and a plurality of vertical wirings arranged in parallel with one another at predetermined intervals and perpendicularly to said horizontal wirings; and

ends of said plurality of horizontal wirings and ends of said plurality of vertical wirings protrude from closest intersections by a length corresponding to a half of a mesh pitch.

4. The clock signal distribution circuit according to claim 2, wherein a part of said mesh wiring is removed, the part corresponding to a region for arranging a macro to be arranged within an area in which said mesh wiring is formed.

5. The clock signal distribution circuit according to claim 4, wherein said mesh wiring protrudes from intersections thereof which face toward the removed part by a predetermined length, so that load to be imposed on said plurality of first clock buffer becomes uniform.

6. The clock signal distribution circuit according to claim 5, wherein:

said mesh wiring is constituted by a plurality of horizontal wirings arranged in parallel with one another at predetermined intervals, and a plurality of vertical wirings arranged in parallel with one another at predetermined intervals and perpendicularly to said horizontal wirings; and

in neighborhood of the removed part of said mesh wiring, ends of said plurality of horizontal wirings and ends of said plurality of vertical wirings protrude from closest intersections by a length corresponding to a half of a mesh pitch.

7. The clock signal distribution circuit according to claim 5, wherein same number of said plurality of second clock buffers are provided to each of a plurality of regions enclosed by the wiring routes of said mesh wiring.

8. The clock signal distribution circuit according to claim 7, wherein among said plurality of second clock buffers, a second clock buffer, to which no target circuit of supplying the clock signal is connected, functions as a dummy buffer in order to keep load to be imposed on said plurality of first clock buffers uniform.

9. The clock signal distribution circuit according to claim 8, wherein said plurality of second clock buffers are connected between intersections of said mesh wiring.

10. The clock signal distribution circuit according to claim 8, wherein said tree wiring comprises at least one branching point at which a wiring route is branched into three routes.

11. The clock signal distribution circuit according to claim 8, wherein the wiring routes of said tree wiring are designed so that an externally supplied clock signal reaches said plurality of first clock buffers substantially at a same time.

12. The clock signal distribution circuit according to claim 8, wherein each of branching points of said tree wiring has a third clock buffer which outputs a clock signal which is synchronous with a clock signal supplied thereto.

13. The clock signal distribution circuit according to claim 12, wherein said third clock buffer which is connected to a first branching point among the branching points of said tree wiring is arranged outside of an area in which said mesh wiring is formed.