Circuit for interfacing a balanced radio frequency power amplifier with an unbalanced load

• US 6,696,902 B2
• Filed: 12/19/2000
• Issued: 02/24/2004
• Est. Priority Date: 12/21/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Lerke, Peter Dam, Riishoej, Jesper
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Glenn, Kimberly E
• Application Number:
  US09/739,234
• Publication Number:
  US 20010004224A1
• Time in Patent Office: 1,162 Days
• Field of Search: 333/25, 333/1, 330/275, 330/301, 330/116, 330/117, 330/69
• US Class Current: 333/25
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03H 7/42 Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns

Abstract

A circuit interfacing a balanced RF power amplifier with unbalanced load has a first shunt inductor and a series capacitor connected to a first output and a first shunt capacitor and series inductor connected to a second output of amplifier. The circuit comprises a second shunt inductor connected to the second output and feeding current to the second output. The first shunt capacitor may correspond to a sum of capacitors required to resonate with the series inductor and second shunt inductor. The second shunt inductor may exceed a value required to resonate with the capacitance of the first shunt capacitor less the capacitance required to resonate with the series inductor, by the same amount as the first shunt inductor exceeds the value required to resonate with the series capacitor. The circuit may further comprise a second shunt capacitor connected to first output, whereby first shunt capacitor exceeds sum of capacitors required to resonate with series inductor and second shunt inductor.

Claims

1. A circuit for interfacing a balanced radio frequency power amplifier including first and second outputs respectively in phase opposition to an unbalanced load comprising:

a first shunt inductor and a series capacitor, the series capacitor being connected on one side to a first output and on another side to the unbalanced load and the first shunt inductor on one side being connected to the first output;

a first shunt capacitor and a series inductor, the series inductor being connected on one side to the second output and on another side to the unbalanced load and the first shunt capacitor on one side being connected to the second output;

a second shunt inductor connected to the second output;

a power supply of the first output;

a power supply of the second output; and

wherein

the series capacitor and the series inductor are part of a flow path to the unbalanced load, the first shunt inductor is part of a flow path from the power supply connected to the first output, and the second shunt inductor is part of a flow path from the power supply connected to the second output and at least one of the first shunt inductor and the series capacitor or the first shunt capacitor and the series inductor form a resonant circuit at or near an operating frequency of the circuit.

2. A circuit according to claim 1, wherein:

a capacitance of the first shunt capacitor approximately corresponds to a sum of a capacitance required to form resonant circuits respectively with the series inductor and the second shunt inductor, at or near an operating frequency of the circuit which is an operating frequency of the balanced radio frequency power amplifier.

3. A circuit according to claim 2, wherein:

the first shunt inductor forms a resonant circuit with the series capacitor at or near the operating frequency of the circuit which is an operating frequency of the balanced radio frequency power amplifier.

4. A circuit according to claim 1, wherein:

an inductance of the second shunt inductor exceeds by a value of inductance required to form a first resonant circuit, at or near an operating frequency of the circuit, with a capacitance of the first shunt capacitor being less than a capacitance required to form a second resonant circuit at or near the operating frequency with the series inductor, and an inductance of the first shunt inductor approximately exceeds a value of inductance required to form a third resonant circuit with the series capacitor at the operating frequency of the circuit which is an operating frequency of the balanced radio frequency power amplifier.

5. A circuit according to claim 1, comprising:

a second shunt capacitor connected to the first output, wherein a capacitance of the first shunt capacitor exceeds a capacitance required to form resonant circuits respectively with the series inductor and the second shunt inductor, at or near the operating frequency of the circuit which is an operating frequency of the balanced radio frequency power amplifier, by an amount approximately corresponding to a capacitance of the second shunt capacitor.

6. A circuit according to claim 5, wherein the first shunt inductor forms a resonant circuit with the series capacitor at or near the operating frequency of the circuit which is an operating frequency of the balanced radio frequency power amplifier.

7. A circuit according to claim 1, wherein:

an inductance of the first and the second shunt inductors are approximately equal.

8. A circuit according to claim 1, wherein:

an inductance of the first and the second shunt inductors are approximately equal.

9. A physical layout of a circuit comprising:

an amplifier with outputs;

first and the second shunt inductors including terminals; and

a surface on which the amplifier and the first and second shunt inductors are mounted; and

wherein

the terminals of the first and second shunt inductors physically farthest, relative to a position of the amplifier and the first and second shunt inductors mounted on the surface from the outputs of the amplifier of the circuit are directly connected to a same node.

10. A circuit according to claim 9, wherein:

conductor rails mounted on the surface are connected to the outputs of the amplifier; and

the same node is a power supply node situated between the conductor rails.

11. A circuit comprising:

an amplifier with outputs;

first and second shunt capacitors including terminals; and

first and second shunt inductors including terminals; and

wherein

the terminals of the first and second shunt inductors physically farthest from the outputs of the amplifier of the circuit are directly connected to a first same node and the terminals of the first and second shunt capacitors physically farthest from the outputs of the amplifier are connected to a second same node.

12. A circuit according to claim 11, comprising:

conductor rails respectively connected to the outputs of the amplifier; and

wherein

the second same node is one of a ground or virtual ground situated between the conductor rails.

13. A circuit according to claim 12, wherein:

an output node is situated halfway between the conductor rails.

14. A circuit according to claim 11, comprising:

conductor rails respectively connected to the outputs of the amplifier; and

wherein

the series capacitor and series inductor include terminals and the terminals of the series capacitor and the series inductor are on a load side thereof connected to a same output node and the same output node is located between conductor rails.

15. A circuit comprising:

an amplifier with outputs;

conductor rails respectively connected to the outputs of the amplifier;

first and the second shunt inductors including terminals;

a series capacitor and a series inductor including terminals; and

wherein

the terminals of the first and second shunt inductors physically farthest from the outputs of the amplifier of the circuit are directly connected to a same node and the terminals of the series capacitor and the series inductor are on a load side thereof are connected to a same node which is located between the conductor rails.

16. A circuit according to claim 15, wherein:

the an output node is situated halfway between the conductor rails.

17. A circuit comprising:

an amplifier with outputs;

conductor rails connected to the outputs of the amplifier;

first and the second shunt inductors including terminals; and

a series capacitor and a series inductor including terminals; and

wherein

the terminals of the first and second shunt inductors physically farthest from the outputs of the amplifier of the circuit are directly connected to first same node which is a power supply node situated between the conductor rails and the terminals of the series capacitor and the series inductor are on a load side thereof of connected to a second same node which is located between the conductor rails.

18. A circuit according to claim 17, wherein:

the second same node is an output node situated halfway between the conductor rails.

19. A circuit for interfacing a balanced radio frequency power amplifier including first and second outputs respectively in phase opposition to an unbalanced load comprising:

a first shunt inductor and a series capacitor, the series capacitor being connected on one side to a first output and on another side to the unbalanced load and the first shunt inductor on one side being connected to the first output;

a first shunt capacitor and a series inductor, the series inductor being connected on one side to the second output and on another side to the unbalanced load and the first shunt capacitor on one side being connected to the second output;

a second shunt inductor connected to the second output;

a power supply of the first output;

a power supply of the second output; and

wherein

the series capacitor and the series inductor are part of a flow path to the unbalanced load, the first shunt inductor is part of a flow path from the power supply connected to the first output, and the second shunt inductor is part of a flow path from the power supply connected to the second output.