Graphics system interface

• US 6,697,074 B2
• Filed: 07/30/2002
• Issued: 02/24/2004
• Est. Priority Date: 11/28/2000
• Status: Active Grant

• Current Assignee: Nintendo Company Limited
• Original Assignee: Nintendo Company Limited
• Inventors: Moore, Robert, Parikh, Vimal, Cheng, Howard
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US10/207,120
• Publication Number:
  US 20030052887A1
• Time in Patent Office: 574 Days
• Field of Search: 345/522, 345/581, 345/503, 345/545, 345/419, 345/427, 345/520, 345/553, 345/559, 709/328, 712/208, 712/210
• US Class Current: 345/522
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 17/00 Three dimensional [3D] modelling, e.g. data description of 3D objects

Abstract

An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Claims

1. A graphics system command stream for use in a graphics system having an internal frame buffer and plurality of pixel engine registers within a graphics pipeline, the graphics system command stream being operable upon execution to set said internal frame buffer, said graphics system command stream comprising:

a stream command 0x614F providing access to said registers and defining a pixel engine copy clear alpha/red command that designates a first register of said plurality of pixel engine registers which contains an alpha value and a red value, herein said first register includes a 1-byte pad, a 1-byte alpha value and a 1-byte red value;

a stream command 0x6150 providing access to said registers and defining a pixel engine copy clear greenlblue command that designates a second regis er of said plurality of pixel engine registers which contains a green value and a blue value, wherein said second register includes a 1-byte pad, a 1-byte green value and a 1-byte blue value; and

a stream command 0x6151 providing access to said registers and defining a pixel engine copy clear z command that designates a third register of said plurality of pixel engine registers which contains a 24-bit z value,

wherein upon execution of the graphics command stream the embedded frame buffer is set with said alpha value, said red value, said green value, said blue and said z value.

2. A computer readable storage medium encoded with an executable command stream for use in a graphics system having an internal frame buffer and plurality of pixel engine registers within a graphics pipeline, the grapics system command stream being operable upon execution to set said internal frame buffer, said storage medium comprising:

a stream command 0x614F providing access to said registers and defining a pixel engine copy clear alpha/red command that designates a first register of said plurality of pixel engine registers which contains an alpha value and a red value, herein said first register includes a 1-byte pad, a 1-byte alpha value and a 1-byte red value;

a stream command 0x6150 providing access to said registers and defining a pixel engine copy clear green/blue command that designates a second register of said plurality of pixel engine registers which contains a green value and a blue value, wherein said second register includes a 1-byte pad, a 1-byte green value and a 1-byte blue value; and

a stream command 0x6151 providing access to said registers and defining a pixel engine copy clear z command that designates a third register of said plurality of pixel engine registers which contains a 24-bit z value,

wherein upon execution of the graphics command stream the embedded frame buffer is set with said alpha value, said red value, said green value, said blue and said z value.

3. For use in a graphics system having an internal frame buffer and plurality of pixel engine registers within a graphics pipeline, a method of setting said internal frame buffer using a graphics system command stream, said method comprising:

generating a stream command 0x614F which provides access to said registers and defines a pixel engine copy clear alpha/red command that designates first register of said plurality of pixel engine registers which contains an alpha value and a red value, wherein said first register includes a 1-byte pad, a 1-byte alpha value and a 1-byte red value;

generating a stream command 0x6150 which provides access to said registers and defines a pixel engine copy clear green/blue command that designate a second register of said plurality of pixel engine registers which contains a green value and a blue value, wherein said second register includes a 1-byte pad, a 1-byte green val e and a 1-byte blue value; and

generating a stream command 0x6151 which provides access to said registers and defines a pixel engine copy clear z command that designates a third register of said plurality of pixel engine registers which contains a 24-bit z value,

wherein upon generation of the command stream the embedded frame buffer is set with said alpha value, said red value, said green value, said blue and said z value.

4. A graphics command stream decoder for use in a graphics system having an internal frame buffer and plurality of pixel engine registers within a graphics pipeline, the decoder being operable to set said internal frame buffer, said decoder comprising:

a first decoding section decoding a stream command 0x614F providing access to said registers and defining a pixel engine copy clear alpha/red command that designates a first register of said plurality of pixel engine registers which contains an alpha value and a red value, wherein said first register includes a 1-byte pad, a 1-byte alpha value and a 1-byte red value;

a second decoding section decoding a stream command 0x6150 providing access to said registers and defining a pixel engine copy clear green/blue command that designates a second register of said plurality of pixel engine registers which contains a green value and a blue value, wherein said second register includes a 1-byte pad, a 1-byte green value and a 1-byte blue value; and

a third decoding section decoding a stream command 0x6151 providing access to said registers and defining a pixel engine copy clear z command that designates a third register of said plurality of pixel engine registers which contains a 24 bit z value,

wherein the embedded frame buffer is set by said decoder with said alpha value, said red value, said green value, said blue and said z value.