Decoder system capable of performing a plural-stage process

• US 6,697,075 B1
• Filed: 09/13/1999
• Issued: 02/24/2004
• Est. Priority Date: 03/27/1997
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Paterson, Kenneth Graham
• Primary Examiner(s): Luu, Matthew
• Assistant Examiner(s): CHUNG, DANIEL J
• Application Number:
  US09/381,010
• Time in Patent Office: 1,625 Days
• Field of Search: 345/660, 345/567, 345/566, 345/565, 345/564, 345/84, 345/568, 358/539, 358/426.01, 358/426.02, 358/426.03, 348/468, 365/230.01, 365/230.04, 365/230.06
• US Class Current: 345/567
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3625 using active addressing
• CPC Class Codes: G09G 3/3629 using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
• CPC Class Codes: G09G 3/3681 suitable for passive matrices only
• CPC Class Codes: G09G 3/3692 suitable for passive matrices only
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Claims

1. A decoder system, comprising:

an address input for receiving an address signal representing any of a plurality of address values (D);

a plurality of intermediate nodes;

a decoder responsive to the address signal and arranged to stimulate, for each address value, a respective combination of the intermediate nodes; and

a plurality of outputs, each responsive to a respective group of the intermediate nodes such that the stimulation applied to that output is dependent upon the stimulation applied by the decoder to each of the intermediate nodes in the respective group;

wherein the decoder is arranged to perform a plural-stage process in determining which of the intermediate nodes to stimulate in response to each address value, said plural-stage process comprising at least a first stage in which results are determined and a second stage for which the results of the first stage are provided as inputs,

wherein the plural-stage process comprises the determination of a word of a predetermined constant weight code;

mapping or representing the address value in accordance with a mathematical structure;

performing one or more operations in the mathematical structure to provide results equivalent to generation of a word of a constant weight code; and

mapping or representing the results from the mathematical structure as a selection of intermediate nodes.

2. A system as claimed in claim 1, wherein the decoder comprises a microprocessor which is programmed to perform the plural-stage process.

3. A system as claimed in claim 1, wherein the decoder comprises hard-wired logic circuitry and/or arithmetic circuitry and/or look-up circuitry arranged to perform the plural-stage process.

4. A system as claimed in claim 1, wherein the mathematical structure is a finite affine geometry.

5. A system as claimed in claim 1, wherein the mathematical structure is a finite projective geometry.

6. A system as claimed in claim 1, wherein the mathematical structure is a difference family and the one or more operations comprise arithmetic operations with sets of elements from a group.

7. A system as claimed in claim 1, wherein the mathematical structure is chosen such that that the one or more operations are in accordance with a concatenation scheme.

8. A system as claimed in claim 1, wherein, in response to each address value, a respective single one of the outputs is stimulated, or stimulated beyond a predetermined threshold.

9. A decoder system, comprising:

an address input for receiving an address signal representing any of a plurality of address values (D);

a plurality of intermediate nodes;

a decoder responsive to the address signal and arranged to stimulate, for each address value, a respective combination of the intermediate nodes; and

a plurality of outputs, each responsive to a respective group of the intermediate nodes such that the stimulation applied to that output is dependent upon the stimulation applied by the decoder to each of the intermediate nodes in the respective group;

wherein the decoder is arranged to perform a plural-stage process in determining which of the intermediate nodes to stimulate in response to each address value, said plural-stage process comprising at least a first stage in which results are determined and a second stage for which the results of the first stage are provided as inputs,

further including a resolution input for receiving a resolution signal representing any of a plurality of resolution values, and wherein the decoder is responsive to the resolution signal such that;

when the resolution signal has a first value, the combination of intermediate nodes stimulated in response to each address value causes a first number of the outputs to be stimulated, or to be stimulated beyond a predetermined threshold; and

when the resolution signal has a second value, the combination of intermediate nodes stimulated in response to each address value causes a group of a second number of the outputs, greater than said first number, to be stimulated, or to be stimulated beyond the threshold.

10. A system as claimed in claim 9, wherein the decoder is responsive to the resolution signal such that when the resolution signal has at least one further value, the combination of intermediate nodes stimulated in response to each address value causes a, or a respective, group of a further number of the outputs, greater than said first number or said second number, to be stimulated, or to be stimulated beyond the threshold.

11. A system as claimed in claim 10, wherein the or each further different number is an integer multiple of said second number.

12. A system as claimed in claim 11, wherein each group, when the resolution signal has said one further value, is a union of a predetermined number of the groups when the resolution signal has said second value.

13. A system as claimed in claim 12, wherein the or each further different number is an integer multiple of said first number.

14. A system as claimed in claim 13, wherein each group, when the resolution signal has said one further value, is a union of a predetermined number of the groups when the resolution signal has said first value.

15. A system as claimed in claim 9, wherein said first number is one.

16. A system as claimed in claim 9, wherein the arrangement is such that the outputs which are so stimulated in response to each address value when the resolution signal has said second value are physically grouped adjacent each other.

17. A system as claimed in claim 9 wherein, in response to each address value, all of the outputs not stimulated beyond the determined threshold are also not stimulated beyond a second determined threshold, lower than the determined threshold.

18. A method of manufacturing a decoder system having the following elements:

an address input for receiving an address signal representing any of a plurality of address values (D);

a plurality of intermediate nodes;

a decoder responsive to the address signal and arranged to stimulate, for each address value, a respective combination of the intermediate nodes; and

a plurality of outputs, each responsive to a respective group of the intermediate nodes such that the stimulation applied to that output is dependent upon the stimulation applied by the decoder to each of the intermediate nodes in the respective group, wherein the decoder is arranged to perform a plural-stage process in determining which of the intermediate nodes to stimulate in response to each address value, said plural-stage process comprising at least a first stage in which results are determined and a second stage for which the results of the first stage are provided as inputs;

wherein the method of manufacturing comprises the steps of;

providing such a decoder which is;

responsive to an address signal representing any of a plurality of address values; and

arranged to stimulate, for each address value, a respective combination of intermediate nodes;

providing a plurality of outputs;

determining, for each output, a respective group of the intermediate nodes to which that output is to be responsive; and

rendering each output responsive to the intermediate nodes in the respective determined group such that the stimulation applied to that output is dependent upon the stimulation applied by the decoder to each of the intermediate nodes in the respective group;

characterised by the steps of;

determining a plural-stage process to be performed by a decoder, said plural-stage process comprising at least a first stage in which results are determined and a second stage for which the results of the first stage are provided as inputs;

arranging the decoder to perform the determined plural-stage process in determining which of the intermediate nodes to stimulate in response to each address value; and

using the determined plural-stage process in said step of determining the group of the intermediate nodes to which the outputs are to be responsive;

wherein the steps of providing such a decoder which is responsive to an address signal representing any of a plurality of address values and arranged to stimulate, for each address value, a respective combination of intermediate nodes, and of determining, for each output, a respective group of the intermediate nodes to which that output is to be responsive are achieved by determination of a constant weight code, wherein words of said constant weight code are used for determining respective combinations of intermediate nodes for each address value, wherein the plural-stage process performed by the decoder comprises the determination of a word of a predetermined constant weight code.

19. A method as claimed in claim 18, wherein the constant weight code is derived through mapping of address values into an affine geometry.

20. A method as claimed in claim 18, wherein the constant weight code is derived through mapping of address values into a projective geometery.

21. A method as claimed in claim 18, wherein the constant weight code is derived through representing the address values as the translates of the sets of a difference family.

22. A method as claimed in claim 18, wherein the constant weight code is derived through the method of concatenation of codes with the address values determining particular codewords used in the concatenation.