Flash memory array structure

• US 6,697,284 B2
• Filed: 08/29/2002
• Issued: 02/24/2004
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marotta, Giulio Giuseppe
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Luu, Pho M.
• Application Number:
  US10/231,449
• Publication Number:
  US 20030058689A1
• Time in Patent Office: 544 Days
• Field of Search: 365/189.03, 365/63, 365/51
• US Class Current: 365/189.03
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A flash memory array structure that has independently operating memory arrays. In one embodiment, a flash memory device comprises a poly silicon layer, a first metal layer and a second metal layer. The poly silicon layer has a plurality of word lines formed therein. The word lines are coupled to rows of memory cells. The first metal layer has a plurality of local bit lines formed therein. The local bit lines are coupled to columns of memory cells. The second metal layer has a plurality of global bit lines formed therein. The global bit lines are selectively coupled to the plurality of local bit lines. The global bit lines are further selectively bisected during manufacture to form a first bank and a second bank of memory cells. The first and second banks allow concurrent memory operations to be performed on the flash memory device.

Claims

1. A flash memory device comprising:

a poly silicon layer having a plurality of word lines formed therein, the word lines are coupled to rows of memory cells;

a first metal layer having a plurality of local bit lines formed therein, the local bit lines are coupled to columns of memory cells; and

a second metal layer having a plurality of global bit lines formed therein, the global bit lines are selectively coupled to the plurality of local bit lines, the global bit lines are further selectively bisected during manufacture to form a first bank and a second bank of memory cells, wherein concurrent memory operations can be performed on the first and second banks.

2. The flash memory device of claim 1 further comprising:

control circuitry to control memory operations to the memory cells, wherein the control circuitry is programmed during manufacture to recognize boundary addresses of the memory cells in the respective first and second banks.

3. The flash memory device of claim 1 wherein the second metal layer containing the global bit lines is the last metal layer to be formed so the size of the first and second banks are created toward the end of the production process of the flash memory device to minimize disruptions.

4. The flash memory device of claim 1 wherein each bank has a pair of quadrants of memory cells separated by a row decoder circuit, wherein each row decoder circuit is used to decode row address requests to the rows of memory cells in its pair of associated quadrants.

5. The flash memory device of claim 4 wherein each quadrant has a stack of erasable sectors of memory cells.

6. The flash memory device of claim 5 wherein the global bit lines are bisected to partition the first and second banks between erasable sectors of memory cells.

7. The flash memory device of claim 4 wherein the number of sectors of memory cells in each quadrant are determined by the location of the bisection of the global bit lines.

8. A non-volatile memory device comprising:

a first and second bank, each bank having a pair of quadrants of non-volatile memory cells, the memory cells in each quadrant are arranged in row and column fashion;

a word line for each row of memory cells in each quadrant, each word line is formed in a poly silicon layer;

a local bit line for each column in each quadrant, each local bit line is formed in a first metal layer; and

a plurality of global bit lines selectively coupled to the local bit lines in each quadrant, the global bit lines are formed in a second metal layer, wherein the global bit lines are disconnected at selected locations to form the first and second bank.

9. The non-volatile memory device of claim 8 wherein concurrent memory operations can occur in the first and second banks.

10. The non-volatile memory device of claim 8 wherein the memory space in each quadrant is determined by the position of the disconnection in the global bit lines.

11. The non-volatile memory device of claim 8 wherein the second metal layer is the last metal layer to be formed in manufacturing the non-volatile device.

12. The non-volatile memory device of claim 8 further comprising:

a chip controller circuit to control memory operations to the memory cells, the chip controller circuit is programmed to set boundary addresses defining the first bank and the second bank.

13. The non-volatile memory device of claim 8 wherein each word line is coupled to a control gate of each memory cell in an associated row of memory cells.

14. The non-volatile memory device of claim 8 wherein each local bit line is coupled to a drain of each memory cell in associated column of memory cells.

15. The non-volatile memory device of claim 8 wherein each quadrant has a sense amplifier circuit and data path circuit.

16. A flash memory device comprising:

a memory array having memory cells arranged in rows and columns;

a word line for each row of memory cells in the memory array, each word line is formed in a poly silicon layer;

a local bit line for each row of memory cells in the memory array, each local bit line is formed in a first metal layer; and

a plurality of global bit lines selectively coupled to the local bit lines, each global bit line is formed in a second metal layer, wherein the global bit lines are selectively bisected to form a first and second bank of memory cells in the memory array to allow concurrent memory operations.

17. The flash memory device of claim 16 further comprising:

control circuitry to control memory operations to the first and second banks, wherein boundary addresses that distinguish the memory cells in an associated bank are programmed in the control circuitry.

18. The flash memory device of claim 17 wherein the boundary addresses programmed in the control circuitry are set via straps coupled to the second metal layer.

19. The flash memory device of claim 16 wherein each bank is divided into a pair of quadrants.

20. The flash memory device of claim 19 further comprising:

a first row decoder circuit coupled between the pair of quadrants in the first bank to route row address requests to the memory cells in the pair of quadrants in the first bank; and

a second row decoder circuit coupled between the pair of quadrants in the second bank to route row address requests to the memory cells in the pair of quadrants in the second bank.

21. The flash memory of claim 19 wherein each quadrant further comprises:

a plurality of individually erasable blocks of memory cells.

22. The flash memory of claim 21 wherein each block is arranged in groups of words, further wherein each word contains a plurality of regular columns of memory cells and a plurality of redundant columns of memory cells.

23. The flash memory of claim 22 wherein the regular columns in each word are further separated into DQ groups and the redundant columns in each word are separated into a RDQ group.

24. The flash memory device of claim 23 wherein each DQ group and each RDQ group of word lines are selectively coupled to an associated sense amplifier in the sense amplifier circuits by a multiplexer.

25. The flash memory device of claim 23 further comprising:

a data path circuit for each quadrant to transfer data to and from the memory cells in the quadrant.

26. The flash memory device of claim 25 further comprising:

a plurality of internal input/output lines coupled to the data path circuitry to transfer data to and from the memory cells, wherein the input/output lines are formed in the second metal layer.

27. A method of forming a flash memory device having a pair of independently operating memory arrays comprising:

bisecting global bit lines at predetermined locations during manufacture of the flash memory device to form independently operating memory arrays.

28. The method of claim 27 wherein each of the memory arrays has its own set of sense amplifiers to read memory cells and data path circuits to transfer data to and from selected memory arrays.

29. The method of claim 27 wherein the global bit lines are formed in a last metal layer of the flash memory device.

30. The method of claim 29 wherein disconnecting the global bit lines further comprises:

masking the last metal layer during formation of the global bit lines to bisect the global bit lines.

31. The method of claim 29 wherein the last metal layer is the last metal layer formed in making the flash memory device.

32. A method of forming a flash memory device comprising:

forming word lines in a poly silicon layer;

forming local bit lines in a first metal layer;

forming global bit lines in a second metal layer, wherein the first metal layer is positioned between the poly silicon layer and the second metal layer; and

masking the second metal layer while the global bit lines are being formed to break the global bit lines at desired locations, wherein a first and second bank of memory cells in the flash memory device is formed.

33. The method of claim 32 further comprising:

coupling sense amplifiers to each bank to read memory cells; and

coupling data path circuits to each bank to transfer data to and from the banks, wherein the banks can perform concurrent operations.

34. The method of claim 32 further comprising:

programming a chip controller circuit to direct address requests to selected memory cells in a desired bank.

35. The method of claim 32 wherein programming the chip controller further comprises:

coupling straps of the second metal layer to the chip controller circuit to set boundary addresses.

36. A method of forming a flash memory device comprising:

forming word lines in a poly silicon layer, wherein the word lines are coupled to gates of memory cells arranged in columns in a memory array;

forming local bit lines in a first metal layer, wherein the local bit lines are coupled to drains of memory cells arranged in rows in the memory array;

forming global bit lines in a second metal layer, wherein the global bit lines are selectively coupled to the local bit lines; and

bisecting the global bit lines at predetermined locations to form a first and second bank in the memory array, wherein concurrent memory operations can be performed on the first and second banks.

37. The method of claim 36 further comprising:

programming control circuitry to recognize the boundaries of the first and second banks.

38. The method of claim 36 further comprising:

dividing each bank into a pair of quadrants.

39. The method of claim 38 further comprising:

coupling a row decoder circuit between the pair of quadrants to decode row addresses of rows in an associated bank.

40. The method of claim 38 further comprising:

coupling a sense amplifier circuit to local bit lines in each quadrant to read the memory cells in each quadrant.

41. The method of claim 38 wherein the location of the bisection of the global bit lines determines the size of the quadrants in the first and second banks.

42. The method of claim 38 further comprising:

coupling a data path circuit to each quadrant to provide a transition path to and from the memory cells in each quadrant.

43. The method of claim 42 wherein the global bit lines are in the data path circuit.