Method for checking a conductive connection between contact points

• US 6,697,291 B2
• Filed: 06/28/2002
• Issued: 02/24/2004
• Est. Priority Date: 06/28/2001
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Frankowsky, Gerd
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US10/185,629
• Publication Number:
  US 20030002369A1
• Time in Patent Office: 606 Days
• Field of Search: 365/201, 702/89, 702/119, 702/85, 324/158.1
• US Class Current: 365/201
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

In order to test, in parallel, semiconductor chips formed on a wafer, functionally identical contact points of the semiconductor chips are connected to column lines, and the rows of the semiconductor chips are selected by selection signal lines. This method is suitable in particular for checking electrically conductive connections between contact points of the semiconductor chips and mating contacts of a test head.

Claims

1. A method for checking a conductive connection between contact points of semiconductor chips formed on a wafer and mating contacts of a test head, the method which comprises:

connecting functionally identical contact points of the semiconductor chips in columns using column lines configured in the test head;

outputting test signals, which are temporally offset, in rows from the semiconductor chips to the column lines; and

detecting and evaluating the test signals, which are temporally offset, from the column lines.

2. The method according to claim 1, which comprises:

initially, connecting the contact points of the semiconductor chips to shift registers; and

connecting the contact points in rows to a respective selection signal line.

3. The method according to claim 2, which comprises:

generating a test bit in each first storage cell of the shift registers by resetting the shift registers;

applying a selection signal having a beginning that is temporally offset by rows; and

shifting each said test bit row by row to outputs of the shift registers, such that when each said test bit arrives at the outputs of the shift registers, test signals are output to the column lines using driver circuits.

4. The method according to claim 1, which comprises:

placing the contact points in a high-impedance state if no test signal is present at the contact points.

5. The method according to claim 1, which comprises:

connecting the contact points to a test signal line; and

applying a test signal to the test signal line, and feeding the test signal in rows, one after another, to the column lines.

6. The method according to claim 5, which comprises:

using switching elements to connect rows of the contact points of the semiconductor chips to a plurality of test signal lines; and

activating the switching elements using a respective selection contact point of the semiconductor chips.

7. The method according to claim 6, which comprises using some of the column lines as the test signal lines.

8. The method according to claim 5, which comprises using one of the column lines as the test signal line.