System and method for accessing multiple groups of peripheral devices

• US 6,697,867 B1
• Filed: 07/25/2000
• Issued: 02/24/2004
• Est. Priority Date: 07/25/2000
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Chong, Fay Jr.
• Primary Examiner(s): EL HADY, NABIL M
• Application Number:
  US09/625,170
• Time in Patent Office: 1,309 Days
• Field of Search: 709/227, 709/228, 709/229, 710/2, 710/20, 710/21
• US Class Current: 709/229
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/068 Hybrid storage device

Abstract

Several systems and methods are described for accessing one of multiple groups of peripheral devices. One of the systems includes a host system, multiple peripheral devices, and a host adapter. The peripheral devices are arranged to form multiple groups, each group including at least one peripheral device. The host system is coupled to the peripheral devices via the host adapter, and accesses the peripheral devices via the host adapter. The peripheral devices of each group receive a group access signal for controlling accesses from the host system. The host adapter includes a control register and signal routing logic. The signal routing logic is coupled to the control register and to each of the groups of peripheral devices. The control register stores a value for selecting one of the groups of peripheral devices. The host system may include a central processing unit (CPU) configured to write the value to the control register. The signal routing logic receives an access signal from the host system and routes the access signal to the group access signal for the group of peripheral devices selected by the value stored in the control register. The group access signal for each of the remaining groups of peripheral devices is deasserted so that the groups of peripheral devices not selected by the value stored in the control register are not accessed (i.e., do not respond to accesses from the host system).

Claims

1. A system, comprising:

a host system;

a plurality of groups of peripheral devices, wherein each group of peripheral devices includes at least one peripheral device, and wherein each group of peripheral devices is configured to receive a group access signal for controlling accesses from the host system to the peripheral devices; and

a host adapter configured for coupling the host system to the plurality of groups of peripheral devices, the host adapter comprising;

a control register for storing a value for selecting one of the groups of peripheral devices; and

signal routing logic coupled to the control register and to each of the groups of peripheral devices, wherein the signal routing logic is coupled to receive an access signal from the host system and route the access signal to the group access signal for the group of peripheral devices selected by the value stored in the control register, and wherein the group access signal for each of the remaining groups of peripheral devices is deasserted so that the groups of peripheral devices not selected by the value stored in the control register do not respond to accesses from the host system.

2. The system as recited in claim 1, wherein each of the peripheral devices is an AT Attachment (ATA) device, and wherein the access signal is an ATA chip select or control signal.

3. The system as recited in claim 2, wherein each of the peripheral devices includes a plurality of registers, and wherein the group access signal is used to select a portion of the registers of the peripheral devices of the selected group.

4. The system as recited in claim 3, wherein the group access signal is asserted in order to select the portion of the registers.

5. The system as recited in claim 1, wherein each group of peripheral devices is connected to a common data bus.

6. The system as recited in claim 5, wherein the common data bus is an AT Attachment (ATA) data bus.

7. The system as recited in claim 1, wherein the plurality of groups is arranged in p groups, and wherein the signal routing logic comprises a 1-to-p demultiplexer coupled to the control register and configured to route the access signal from the host system to the selected group dependent upon the value stored in the control register.

8. The system of claim 1, wherein the host system comprises a central processing unit (CPU), and wherein the CPU is configured to write the value to the control register.

9. A host adapter for interfacing a host system to a plurality of groups of peripheral devices, wherein each group of peripheral devices includes at least one peripheral device, and wherein each group of peripheral devices is configured to receive a group access signal for controlling accesses from the host system to the peripheral devices, the host adapter comprising:

a control register for storing a value for selecting one of the groups of peripheral devices; and

signal routing logic coupled to the control register and to each of the groups of peripheral devices, wherein the signal routing logic is coupled to provide the group access signal to the group of peripheral devices selected by the value stored in the control register, and wherein the group access signal for each of the remaining groups of peripheral devices is deasserted so that the groups of peripheral devices not selected by the value stored in the control register do not respond to accesses from the host system.

10. The host adapter as recited in claim 9, wherein each peripheral device is an AT Attachment (ATA) device, and wherein the group access signal is an ATA chip select or control signal.

11. The host adapter as recited in claim 9, wherein the plurality of groups is arranged in p groups, and wherein the signal routing logic comprises a 1-to-p demultiplexer coupled to the control register and configured to route an access signal from the host to the selected group dependent upon the value stored in the control register.

12. An AT Attachment (ATA) host adapter for interfacing a host system to a plurality of groups of ATA devices, wherein each group of ATA devices includes at least one ATA device, and wherein each group of ATA devices is configured to receive an ATA chip select 0 (CS0) signal and an ATA chip select 1 (CS1) signal for controlling accesses from the host system to the ATA devices according to an ATA standard, the ATA host adapter comprising:

a control register for storing a value for selecting one of the groups of ATA devices; and

signal routing logic coupled to the control register and to each of the groups of ATA devices, wherein the signal routing logic is coupled to provide the

CS0 signal and CS1 signal to the group of ATA devices selected by the value stored in the control register, and wherein the CS0 signal and CS1 signal for each of the remaining groups of ATA devices are deasserted so that the groups of ATA devices not selected by the value stored in the control register do not respond to accesses from the host system.

13. The ATA host adapter as recited in claim 12, wherein each ATA device comprises either a hard disk drive, a CD-ROM drive, a tape drive, or a DVD drive.

14. The ATA host adapter as recited in claim 12, wherein each of the ATA devices includes a plurality of registers, and wherein the registers of each ATA device are partitioned to form a control portion and a command portion, and wherein the CS0 signal is asserted in order to select the control portion, and wherein the CS1 signal is asserted in order to select the command portion.

15. The ATA host adapter as recited in claim 12, wherein all of the ATA devices are connected to a common ATA bus which is not used to convey the CS0 and CS1 signals.

16. The ATA host adapter as recited in claim 12, wherein the groups of ATA devices are arranged to form p groups, and wherein the signal routing logic comprises:

a first 1-to-p demultiplexer coupled to the control register and configured to route the CS0 signal to the ATA devices of the group selected by the value stored in the control register; and

a second 1-to-p demultiplexer coupled to the control register and configured to route the CS1 signal to the ATA devices of the group selected by the value stored in the control register.

17. A method for accessing a group of peripheral devices, wherein the group is one of

a plurality of groups of peripheral devices, and wherein each group includes at least one peripheral device, and wherein each group is configured to receive a different group access signal for controlling access to the group, the method comprising:

selecting the group of peripheral devices from among the plurality of groups of peripheral devices;

asserting an access signal;

routing the access signal to the groups of peripheral devices such that;

(i) the asserted access signal is provided as the group access signal for the selected group of peripheral devices, and (ii) the group access signal received by the remaining groups of peripheral devices is deasserted;

wherein a value stored in a control register selects the group of peripheral devices from among the plurality of groups of peripheral devices; and

wherein the routing comprises routing the access signal to the group of peripheral devices selected by the value stored in the control register.

18. A method for accessing a group of AT Attachment (ATA) devices, wherein the group is one of a plurality of groups of ATA devices, wherein each group includes at least one ATA device, the method comprising:

storing a value in a control register for selecting the group of ATA devices from among the plurality of groups of ATA devices;

generating an ATA standard chip select 0 (CS0) signal and an ATA standard chip select 1 (CS1) signal such that either the CS0 signal or the CS1 signal is asserted;

routing the CS0 and CS1 signals from said generating to the ATA devices dependent upon the value stored in the control register such that the generated CS0 and CS1 signals are provided to the ATA devices of the group selected by said value, and wherein the ATA devices of groups not selected by said value receive deasserted CS0 and CS1 signals such that ATA devices of the groups not selected by said value do not respond to ATA accesses.