Synchronous content addressable memory

• US 6,697,911 B2
• Filed: 02/06/2001
• Issued: 02/24/2004
• Est. Priority Date: 10/30/1997
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Nataraj, Bindiganavale S., Khanna, Sandeep, Srinivasan, Varadarajan
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US09/778,170
• Publication Number:
  US 20010005876A1
• Time in Patent Office: 1,113 Days
• Field of Search: 711/108, 380/9, 380/5, 365/49, 365/226
• US Class Current: 711/108
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells. The status information may include a match flag, multiple match flag, full flag, skip bit, empty bit, or a device identification for the CAM device.

Claims

1. A method of reading data from a synchronous content addressable memory (CAM) device, comprising:

instructing the CAM device to compare comparand data with data stored in a plurality of first CAM cells;

comparing the comparand data with the data stored in each of the plurality of first CAM cells;

sensing data stored in a second CAM cell; and

outputting the sensed data from the CAM device, wherein the instructing, comparing, sensing, and outputting occur in less than three clock cycles.

2. The method of claim 1, further comprising determining a match address for at least one of the plurality of first CAM cells storing data matching the comparand data.

3. The method of claim 2, wherein the sensing further comprises outputting status information corresponding to the at least one of the plurality of first CAM cells storing data matching the comparand data.

4. The method of claim 1, wherein the instructing, comparing, sensing and outputting occur in the same clock cycle.

5. A method of reading data from a synchronous content addressable memory (CAM) device, comprising:

instructing the CAM device to compare comparand data with data stored in a plurality of first CAM cells;

comparing the comparand data with the data stored in the plurality of first CAM cells;

determining a match address for at least one of the plurality of CAM cells storing data matching the comparand data; and

outputting the match address from the CAM device, wherein the instructing, comparing, determining, and outputting occur in less than three clock cycles.

6. The method of claim 5, wherein the instructing, comparing, determining and outputting occur in the same clock cycle.

7. A method of reading data from a synchronous content addressable memory (CAM) device, comprising:

instructing the CAM device to compare comparand data with data stored in a plurality of first CAM cells;

comparing the comparand data with the data stored in the plurality of first CAM cells;

determining that the comparand data matches data stored in one of the plurality of first CAM cells;

sensing validity information from a second CAM cell, wherein the second CAM cell corresponds to the one of the plurality of first CAM cells storing data that matches the comparand data; and

outputting the validity information from the CAM device, wherein the instructing, comparing, determining, sensing, and outputting occur in less than three clock cycles.

8. The method of claim 7, wherein the validity information comprises a skip bit.

9. The method of claim 7, wherein the validity information comprises an empty bit.

10. The method of claim 7, wherein the instructing, comparing, determining, sensing and outputting occur in the same clock cycle.

11. A method of reading data from a synchronous content addressable memory (CAM) device, comprising:

instructing the CAM device to compare comparand data with data stored in a plurality of first CAM cells;

comparing the comparand data with the data stored in the plurality of first CAM cells;

sensing data stored in a second CAM cell;

loading the sensed data into a status register, wherein the instructing, comparing, sensing, and loading all occur in a first clock cycle; and

outputting the sensed data from the status register in a second clock cycle.

12. The method of claim 11, further comprising the determining a match address for at least one of the plurality of first CAM cells storing data matching the comparand data, wherein the loading further comprises loading the match address into the status register in the first clock cycle.

13. The method of claim 12, further comprising outputting the sensed data and the match address from the status register in a second clock cycle.

14. A method of reading data from a synchronous content addressable memory (CAM) device, comprising:

instructing the CAM device to compare comparand data with data stored in a plurality of CAM cells;

comparing the comparand data with the data stored in the plurality of CAM cells;

determining a match address for at least one of the plurality of CAM cells storing data matching the comparand data;

loading the match address into a status register, wherein the instructing, comparing, determining, and loading all occur in a first clock cycle; and

outputting the match address from the storage element in a second clock cycle.