System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry
First Claim
1. A computer system including a microprocessor on a single integrated circuit chip having on-chip circuitry comprising a CPU with a plurality of registers and at least one other module, said integrated circuit chip further comprising a communication bus providing a parallel communication path between said CPU and said at least one other module, said at least one other module having logic circuitry connected to said bus, the on-chip circuitry being operable to receive on said bus digital data packets including control bits and said at least one other module being operable to receive the packets and respond thereto independently of operation of the CPU, wherein said digital data packets include packets with a destination identification for use on said bus and an address identification for use within the at least one other module forming the destination, said integrated circuit chip further comprising an external communication port connected to said bus, said external communication port having an internal signal connection to said bus and having translation circuitry and an external signal connection, said internal signal connection having an internal parallel format for said digital data packets including said control bits, said external signal connection having an external parallel format for said digital signal packets including said control bits, said external parallel format having a lesser bit width than said internal parallel format, and said translation circuitry to effect translating of digital signal packets between said internal and external formats, wherein said translating provides a one-to one correspondence between data of said internal and external formats, said external communication port being operable independently of operation of said CPU.
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Abstract
There is disclosed a computer system including a microprocessor on a single integrated circuit chip comprising an on-chip CPU and a communication bus providing a parallel communication path between the CPU and at least one of the module with logic circuitry. The integrated circuit device further comprises an external communication port connected to the bus, having an internal parallel format for connection to the bus. The external port further has an external signal having an external format less parallel than the internal format. Translation circuitry is provided to effect conversion between said internal and external formats. There is also disclosed a method of operating such a computer system.
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Citations
17 Claims
- 1. A computer system including a microprocessor on a single integrated circuit chip having on-chip circuitry comprising a CPU with a plurality of registers and at least one other module, said integrated circuit chip further comprising a communication bus providing a parallel communication path between said CPU and said at least one other module, said at least one other module having logic circuitry connected to said bus, the on-chip circuitry being operable to receive on said bus digital data packets including control bits and said at least one other module being operable to receive the packets and respond thereto independently of operation of the CPU, wherein said digital data packets include packets with a destination identification for use on said bus and an address identification for use within the at least one other module forming the destination, said integrated circuit chip further comprising an external communication port connected to said bus, said external communication port having an internal signal connection to said bus and having translation circuitry and an external signal connection, said internal signal connection having an internal parallel format for said digital data packets including said control bits, said external signal connection having an external parallel format for said digital signal packets including said control bits, said external parallel format having a lesser bit width than said internal parallel format, and said translation circuitry to effect translating of digital signal packets between said internal and external formats, wherein said translating provides a one-to one correspondence between data of said internal and external formats, said external communication port being operable independently of operation of said CPU.
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9. A method of operating a computer system comprising a microprocessor on a single integrated circuit chip having an on-chip CPU, a plurality of registers, a communication bus providing a parallel communication path between said CPU and at least one other module with logic circuitry connected to said bus, and an external communication port connected to said bus, and having an external signal connection, said method comprising:
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generating on said bus digital signal packets including control bits, wherein said digital signal packets include packets with a destination identification for use on said bus and an address identification for use within the at least one other module forming the destination;
receiving at said at least one other module a packet on the bus and responding thereto independently of operation of the CPU;
supplying from said bus to said external communication port a packet having an internal parallel format, and translating the packet in the external communication port independently of the operation of the CPU to a digital signal packet, including control bits, said digital signal packet having an external parallel format for said external signal connection, said external parallel format having a lesser bit width than said internal parallel format; and
supplying from said external signal connection to said external communication port a packet having said external parallel format, translating the packet in the external communication port independently of the CPU to a digital signal packet including control bits, said packet having said internal parallel format, and supplying said packet in said internal parallel format to said bus, whereby said translating provides a one-to-one equivalence between data of said internal and external formats. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A computer system including a microprocessor on a single integrated circuit chip having on-chip circuitry comprising:
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a CPU with a plurality of registers;
at least one other module;
a communication bus providing a parallel communication path between said CPU and said at least one other module, said at least one other module having logic circuitry connected to said bus, the on-chip circuitry being operable to receive on said bus digital data packets including control bits and said at least one other module being operable to receive the packet and respond thereto independently of operation of the CPU, wherein said digital data packets include packets with a destination identification for use on said bus and an address identification for use within the at least one other module forming the destination;
an external communication port connected to said bus, said external communication port having an internal signal connection to said bus, said internal signal connection having an internal parallel format for digital data packets including control bits, an external signal connection having a serial format for said digital data packets including said control bits, and translation circuitry to effect translating of said digital data packets in said internal format into said external format, whereby said translating provides a one-to-one equivalence between said packets in said internal and external formats, said external communication port being operable independently of operation of said CPU.
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17. A method of operating a computer system comprising a microprocessor on a single integrated circuit chip with an on-chip CPU, a plurality of registers, a communication bus providing a parallel communication path between said CPU and at least one other module having logic circuitry connected to said bus, and an external communication port connected to said bus and having an external signal connection, said method comprising:
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generating, on said bus, digital signal packets including control bits, wherein said digital signal packets include packets with a destination identification for use on said bus and an address identification for use within the at least one other module forming the destination;
receiving, at said at least one other module, a packet on the bus and responding thereto independently of the operation of the CPU; and
supplying from said bus to said external communication port a packet having an internal parallel format, translating the packet in the external communication port independently of the CPU to a digital signal packet including control bits, said digital signal packet having an external serial format for said external signal connection;
supplying from said external signal connection to said external communication port a packet having said external serial format;
translating the packet in the external communication port independently of the CPU to a digital signal packet including control bits, said packet having said internal parallel format; and
supplying said packet in said internal parallel format to said bus, whereby said step of translating provides a one-to-one equivalence between said packets in said internal and external formats.
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Specification