Emulation circuit with a hold time algorithm, logic analyzer and shadow memory

• US 6,697,957 B1
• Filed: 05/11/2000
• Issued: 02/24/2004
• Est. Priority Date: 05/11/2000
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Shei, Swey-Yan, Wang, Ming Yang, Carrell, William C.
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/569,695
• Time in Patent Office: 1,384 Days
• Field of Search: 713/1, 713/100, 713/400, 713/401, 713/503, 713/600
• US Class Current: 713/401
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

Claims

1. An integrated circuit logic element for implementing reconfigurable logic comprising:

an input line that inputs a signal into the logic element;

a lookup table coupled to the input line that receives the inputted signal and outputs a first data on a first output line;

a delay circuit being configured to be selectively activated and being configured to receive the first data on the first output line and to output a delayed first data, the delayed first data being the first data delayed by a selectable amount;

a data latch coupled to the delay circuit that receives the delayed first data and outputs a second data on its output; and

an output line that receives one of the first data, delayed first data, or the second data and passes it out of the logic element.

2. The logic element of claim 1 wherein the delay circuit includes a flip flop.

3. The logic element of claim 2 wherein the flip flop is edge triggered.

4. The logic element of claim 1 wherein the delay circuit includes a plurality of flip flops connected in series.

5. The logic element of claim 4 wherein the plurality of flip flops are edge triggered.

6. The logic element of claim 1 further comprising a clock that provides a clock signal to the delay circuit and a clock adjuster that adjusts the speed of the clock signal to vary the amount of delay generated by the delay circuit.

7. The logic element of claim 1 further comprising a first clock coupled to the lookup table and a second clock that is faster than the first clock and is coupled to the delay circuit.

8. The logic element of claim 1 further comprising a selection circuit coupled to the lookup table, the delay circuit and the data latch, the selection circuit receiving the first data, delayed first data, and the second data and passing one of the first data, delayed first data, and the second data to the output line.

9. The logic element of claim 1 further comprising a selection circuit coupled to the lookup table, the delay circuit and the data latch, the selection circuit receiving the first data and the delayed first data and passing one of the first data or delayed first data to the data latch.

10. The logic element of claim 1 further comprising a plurality of input lines and a multiplexer for selecting one of the input lines for passing a signal to control the data latch.

11. The logic element of claim 1 wherein the data latch functions as either a latch or a flip-flop.

12. The logic element of claim 1 wherein the data latch receives a set signal on a first pin which sets the output of the data latch to one logic state and a reset signal on a second pin which resets the output of the data latch to another logic state, the first pin being separate from the second pin.

13. The logic element of claim 1 wherein the data latch comprises a master flip flop and a slave flip flop connected in series.

14. The logic element of claim 1 further comprising an input sharing circuit coupled to the input line, the input sharing circuit permitting the logic element to share an input with another logic element.

15. The logic element of claim 14 further comprising a random access memory coupled to the input line, the input sharing circuit permitting the logic element to share data in the random access memory with another logic element.

16. The logic element of claim 14 wherein the input sharing circuit includes a line for passing data from the logic element to another logic element.

17. The logic element of claim 15 wherein the input sharing circuit includes a line for passing data from the random access memory of the logic element to another logic element.

18. The logic element of claim 17 wherein the input sharing circuit includes a line for receiving data from the random access memory of another logic element.

19. The logic element of claim 18 wherein the input sharing circuit receives data from the random access memory of another logic element and stores the data into the random access memory of the logic element.

20. The logic element of claim 14 wherein the input sharing circuit includes a multiplexer for routing the signal from the input line to the logic element.

21. The logic element of claim 1 wherein the lookup table receives at least five inputs.

22. The logic element of claim 1 wherein the lookup table receives six inputs.

23. An integrated circuit logic element for implementing reconfigurable logic comprising:

an input line that inputs a signal into the logic element;

a random access memory coupled to the input line to receive the inputted signal and outputs a first data on a first output line;

a delay circuit being configured to be selectively activated and being configured to receive the first data on the first output line and to output a delayed first data, the delayed first data being the first data delayed by a selectable amount;

a second memory coupled to the random access memory;

a data latch coupled to the random access memory which receives the first data and outputs a second data on its output; and

an output line that receives either the first data, the delayed first data, or the second data and passes it out of the logic element.

24. The logic element of claim 23 wherein the second memory reads data in the random access memory and stores a copy of the data in the second memory.

25. The logic element of claim 23 wherein the second memory samples data from the random access memory and stores the sampled data in the second memory.

26. The logic element of claim 25 wherein the second memory includes a plurality of memory blocks, each memory block storing a different sampled data from the random access memory.

27. The logic element of claim 26 wherein the data stored in the second memory may be read out to the user.

28. The logic element of claim 23 the sampled data stored in the memory blocks of the second memory may be read out in sequence to the user.

29. The logic element of claim 23 further comprising a delay circuit that receives the first data on the first output line and outputs a delayed first data, the delayed first data being the first data delayed by a selectable amount.

30. The logic element of claim 29 wherein the delay circuit includes a flip flop.

31. The logic element of claim 30 wherein the flip flop is edge triggered.

32. The logic element of claim 29 wherein the delay circuit includes a plurality of flip flops connected in series.

33. The logic element of claim 32 wherein the plurality of flip flops are edge triggered.

34. The logic element of claim 29 further comprising a clock that provides a clock signal to the delay circuit and a clock adjuster that adjusts the speed of the clock signal to vary the amount of delay generated by the delay circuit.

35. The logic element of claim 29 further comprising a first clock coupled to the random access memory and a second clock that is faster than the first clock and is coupled to the delay circuit.

36. The logic element of claim 23 further comprising a selection circuit coupled to the random access memory and the data latch, the selection circuit receiving the first data and the second data and passing one of the first data and the second data to the output line.

37. The logic element of claim 29 further comprising a selection circuit coupled to the random access memory, the delay circuit and the data latch, the selection circuit receiving the first data, the delayed first data and the second data and passing one of the first data, the delayed first data or the second data to the output line.

38. The logic element of claim 23 wherein the data latch functions as either a latch or a flip-flop.

39. The logic element of claim 23 wherein the data latch receives a set signal on a first pin which sets the output of the data latch to one logic state and a reset signal on a second pin which resets the output of the data latch to another logic state, the first pin being separate from the second pin.

40. The logic element of claim 23 further comprising an input sharing circuit coupled to the input line, the input sharing circuit permitting the logic element to share an input with another logic element.

41. The logic element of claim 40 wherein the input sharing circuit permits the logic element to share data in the random access memory with another logic element.

42. The logic element of claim 40 wherein the input sharing circuit includes a line for passing data from the logic element to another logic element.

43. The logic element of claim 41 wherein the input sharing circuit includes a line for passing data from the random access memory of the logic element to another logic element.

44. The logic element of claim 43 wherein the input sharing circuit includes a line for receiving data from the random access memory of another logic element.

45. The logic element of claim 44 wherein the input sharing circuit receives data from the random access memory of another logic element and stores the data into the random access memory of the logic element.

46. The logic element of claim 23 further comprising a lookup table that is coupled to the input line, receives at least five inputs and outputs the first data on the first output line.

47. The logic element of claim 46 wherein the lookup table receives six inputs.