Data bus for a plurality of nodes

• US 6,697,966 B1
• Filed: 11/08/2000
• Issued: 02/24/2004
• Est. Priority Date: 03/10/1998
• Status: Expired due to Term

• Current Assignee: Bayerische Motoren Werke AG
• Original Assignee: Bayerische Motoren Werke AG
• Inventors: Griessbach, Robert, Smuk, Karel, Berwanger, Josef, Peller, Martin
• Primary Examiner(s): Baderman, Scott
• Application Number:
  US09/623,853
• Time in Patent Office: 1,203 Days
• Field of Search: 714/43, 714/45, 714/56, 709/252, 709/253, 710/106
• US Class Current: 714/43
• CPC Class Codes: H04L 12/44 Star or tree networks
• CPC Class Codes: H04L 41/0677 Localisation of faults
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0817 by checking functioning

Abstract

A data bus for establishing a connection among a plurality of nodes and having configuration whereby optical data messages are converted to an electrical signal and sent through a logical decision gate to each of the nodes. A memory element, which is connected in parallel to the input of the logic decision gate, provides an addressable manner of monitoring data traffic on the data bus and identifying a source of any malfunction.

Claims

1. A data bus arrangement for a plurality of nodes configured to provide communication among each of said nodes, said data bus arrangement comprising:

a logic decision gate having a plurality of inputs which correspond to said plurality of nodes;

a plurality of optical transmission modules corresponding to said nodes wherein an output of each of said nodes is connected to an input of one of said modules and wherein an output of each said one module provides an electrical signal to a corresponding one of said inputs of said logic decision gate and wherein the output of said logic decision gate is connected in parallel to a respective second input of each of said optical transmission modules;

a plurality of storage elements wherein each of said storage elements is connected in parallel to one of said inputs of said logic decision gate and wherein a state of each of said storage element is permanently changed when an input to said storage element is received.

2. The arrangement according to claim 1, wherein said storage elements are addressable.

3. The arrangement according to claim 1, further including a microcontrollor for reading the state of said storage element.

4. The arrangement according to claim 1, wherein each of said storage elements are resettable.

5. A data bus structure for connecting a plurality of nodes to each other, said structure comprising:

a logic decision gate having a plurality of inputs corresponding to said plurality of nodes;

a plurality of signal converting means, each connected between one of said nodes and one of said inputs of said logic gate, wherein an output of each of said converter means provides an electrical signal as said input to said logic decision gate and wherein an output of said logic decision gate is connected to an input to each of said plurality of signal converting means;

addressable memory means connected in parallel to said output of said converter means for determining and locating a fault occurring during transmission of a message from one of said nodes to another one of said nodes.

6. A system according to claim 5, further including a means for resetting said addressable memory means.