Method of repairing integrated circuits

• US 6,697,979 B1
• Filed: 06/21/2000
• Issued: 02/24/2004
• Est. Priority Date: 12/22/1997
• Status: Expired due to Term

• Current Assignee: Maren Krass, Thomas Richter
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, Münch, Robert
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/598,926
• Time in Patent Office: 1,343 Days
• Field of Search: 714/10, 714/5, 714/732, 714/733, 714/724, 712/10, 712/2
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 29/78 using programmable devices

Abstract

An arrangement and a method are provided for replacing defective units, which can be any desired unit of a chip (e.g., arithmetic and logic units), with a function unit. The arrangement and the method provide for performing self-tests more easily, less expensively and before or during a running of an application program. Fault tolerance is greatly enhanced during operation, which is advantageous for failure-critical applications such as in power plants, aviation, space travel or the military, for example.

Claims

1. An integrated circuit arrangement, comprising:

a plurality of modules, each of the modules having at least one input and at least one output, each of the modules forming at least one cell, the at least one cell including at least one of a bus system, an arithmetic and logic unit and a configurable logic cell;

a supplementary module assigned to at least one of the modules;

at least one input multiplexer coupled upstream to the inputs of the modules, each of the at least one input multiplexers configured to switch, in each case, an input signal between one a first one of the modules and a second one of the modules;

at least one output multiplexer coupled downstream from the outputs of the modules, the at least one output multiplexer configured to switchably receive, in each case, an output signal of the first one of the modules and an output signal of the second one of the modules; and

a control configured to control the at least one input multiplexer and the at least one output multiplexer to exclude a defective one of the modules, the control using a single decoder to perform at least one of (A) switching all of the at least one input multiplexer and the at least one output multiplexer in the same direction, and (B) switching all of the at least one input multiplexer and the at least one output multiplexer so that two groups of consecutive multiplexers are formed, multiplexers within each of the groups being switched in the same direction, the two groups being switched in different directions, the control performing the switching so that the defective one of the module is excluded.

2. The integrated circuit arrangement according to claim 1, wherein the error is detected via self-testing.

3. The integrated circuit arrangement according to claim 1, wherein the control is configured to decode a binary value so as to yield at least one of the first group and the second group.

4. The integrated circuit arrangement according to claim 1, wherein the control is configured to encode a binary value, the binary value defining at least one of a switching element group and a switching element circuit.

5. The integrated circuit arrangement according to claim 4, wherein the binary value is provided via a look-up-table arrangement.

6. The integrated circuit arrangement according to claim 1, further comprising:

a memory that stores a binary value, the binary value indicating at least one of the defective module and all defective modules.

7. An integrated circuit arrangement, comprising:

at least one module including one of an individual module and a plurality of ordered modules, each module of the at least one module having at least one input and at least one output, the at least one module forming at least one cell, the at least one cell including at least one of a bus system, an arithmetic and logic unit and a configurable logic cell;

a supplementary module assigned to the at least one module and being of a same kind as the at least one module;

a first switching element coupled to the at least one input of a particular module and being upstream from the at least one input of the particular module, the first switching element switching an input signal to at least one of the particular module and a module following the particular module; and

a second switching element coupled to the at least one output of the particular module and being downstream from the at least one output of the particular module,

wherein, if an error occurs in a module, then at least one of a defective module and a defective function cell is replaced by a module following the at least one of the defective module and the defective function cell by switching the first switching element and by switching the second switching element, a last module being replaced by the supplementary module, and wherein the binary value is generated by a counter.

8. An integrated circuit arrangement, comprising:

at least one module including one of an individual module and a plurality of ordered modules, each module of the at least one module having at least one input and at least one output, the at least one module forming at least one cell, the at least one cell including at least one of a bus system, an arithmetic and logic unit and a configurable logic cell;

a supplementary module assigned to the at least one module and being of a same kind as the at least one module;

a first switching element coupled to the at least one input of a particular module and being upstream from the at least one input of the particular module, the first switching element switching an input signal to at least one of the particular module and a module following the particular module;

a second switching element coupled to the at least one output of the particular module and being downstream from the at least one output of the particular module; and

a memory that stores a binary value, the binary value indicating at least one of the defective module and all defective modules;

wherein, if an error occurs in a module, then at least one of a defective module and a defective function cell is replaced by a module following the at least one of the defective module and the defective function cell by switching the first switching element and by switching the second switching element, a last module being replaced by the supplementary module, and wherein the memory that stores a binary value is independent of a system start.

9. A method for testing an integrated circuit having cells, comprising the steps of:

testing a cell function of the integrated circuit by executing, with the cells, a test program including calculating test vectors;

performing, with at least one of the cells wired as a comparator, a comparison between a test result and a setpoint result; and

indicating an error if the comparison indicates a deviation between the setpoint result and the test result so that, in response to the error, a module having the cell found to be defective is replaced.

10. The method according to claim 9, wherein the step of testing the cell function includes the step of calling up test data from an integrated memory in the integrated circuit, the test data being used for executing the test program.

11. The method according to claim 9, wherein the method for testing the integrated circuit is carried out at a system start.

12. The method according to claim 9, wherein the method for testing the integrated circuit is carried out as a self-test method of application programs running during at least one of a wait cycle and an IDLE cycle.

13. The method according to claim 12, wherein the self-test method is at least one of called up from an application program and integrated into an application program.

14. The method according to claim 9, further comprising the steps of:

saving data from arithmetic and logic units to a chip-internal memory before running a test algorithm; and

loading data back into the arithmetic and logic units after running the test algorithm.

15. The method according to claim 14, further comprising the steps of:

shutting down registers in the arithmetic and logic units before running the test algorithm;

using test registers for the test algorithms; and

connecting the registers in the arithmetic and logic units after running the test algorithm.

16. The method according to claim 9, further comprising the steps of:

assigning at least one additional supplementary module to a number of ordered modules forming the cells, the at least one additional supplementary module and the ordered modules being of the same kind, each module having at least one input and at least one output;

coupling a first switching element to the at least one input of a particular module, the first switching element being disposed upstream from the at least one input of the particular module, the first switching element being configured to switch an input signal to one of the particular module and a module following the particular module;

coupling a second switching element to the at least one output of the particular module, the second switching element being disposed downstream from the at least one output of the particular module, the second switching element being configured to receive an output from one of the particular module and the module following the particular module; and

if an error is detected in a module, then replacing a defective module by a module following the defective module by switching the first switching element and the second switching element, a last module in the ordered modules being replaced by the supplementary module.

17. A method for testing an integrated circuit having cells, comprising the steps of:

testing a cell function of the integrated circuit by executing, with the cells, a test program including calculating test vectors;

performing, with at least one of the cells, a comparison between a test result and a setpoint result; and

indicating an error if the comparison indicates a deviation between the setpoint result and the test result so that, in response to the error, a module having the cell found to be defective is replaced;

wherein the step of testing the cell function includes the step of testing a cell array by at least one of exchanging and mirroring a test algorithm that includes a plurality of calculations at least once within the cell array.