Method for producing a gate

• US 6,699,755 B1
• Filed: 03/24/2003
• Issued: 03/02/2004
• Est. Priority Date: 03/24/2003
• Status: Active Grant

• Current Assignee: Nexchip Semiconductor Corporation
• Original Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Inventors: Chen, Chun-Yuan, Chiou, Da-Yen
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US10/249,212
• Time in Patent Office: 344 Days
• Field of Search: 438/300, 438/301, 438/201, 438/258, 438/261, 438/719, 438/587
• US Class Current: 438/258
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A method for producing a gate on a semiconductor substrate. The semiconductor substratehas a first oxide layer, a conductive layer, a silicide layer, and a hard mask formed thereon. The method includes defining the hard mask to form a pattern of the gate, performing an etching process to remove portions of the silicide layer and the conductive layer which are not covered by the hard mask, performing an O₂ flush process to form a second oxide layer on the surface of the exposed first oxide layer, and performing a wet etching process to remove portions of the silicide layer to of give sidewalls of the silicide layer a concave shape and to etch back the second oxide layer.

Claims

1. A method for producing a gate on a semiconductor substrate wherein a first oxide layer, a conductive layer, a silicide layer, and a hard mask are formed on the semiconductor substrate, the method comprising:

defining the hard mask to form a pattern of the gate;

performing an etching process to remove portions of the silicide layer and the conductive layer which are not covered by the hard mask so as to expose portions of the first oxide layer;

performing an O₂ flush process to form a second oxide layer on the surface of the exposed first oxide layer; and

performing a wet etching process to remove a portion of the silicide layer to give sidewalls of the silicide layer a concave shape and to etch back the second oxide layer.

2. The method of claim 1 wherein the first oxide layer serves as a gate oxide layer of the gate, and the first oxide layer comprises silicon dioxide(SiO₂).

3. The method of claim 1 wherein the conductive layer comprises a doped polysilicon layer.

4. The method of claim 1 wherein the etching process is a dry etching process.

5. A method for producing a metal oxide semiconductor (MOS) transistor on a semiconductor substrate, the method comprising:

forming a first oxide layer, a conductive layer, a silicide layer, and a hard mask sequentially;

defining the hard mask to form a gate pattern of the MOS transistor;

performing an etching process to remove portions of the silicide layer and the conductive layer which are not covered by the hard mask so as to expose portions of the first oxide layer;

performing an O₂ flush process to form a second oxide layer on the surface of the exposed first oxide layer;

performing a wet etching process to remove a portion of the silicide layer to give sidewalls of the silicide layer a concave shape and to etch back the second oxide layer for forming the gate structure of the MOS transistor; and

performing an first ion implantation process to form a lightly doped drain (LDD) in the semiconductor substrate.

6. The method of claim 5 wherein the first oxide layer serves as a gate oxide layer of the gate, and the first oxide layer comprises a silicon dioxide.

7. The method of claim 5 wherein the first oxide layer not covered by the gate serves a pad oxide layer for reducing damage of the surface of the semiconductor substrate due to the ion implantation process.

8. The method of claim 5 wherein the conductive layer comprises a doped polysilicon layer.

9. The method of claim 5 wherein the etching process is a dry etching process.

10. The method of claim 5 wherein the MOS transistor serves as a pass transistor of a memory cell of a dynamic random access memory (DRAM).

11. The method of claim 5 further comprising a second ion implantation processfor forming a source and a drain of the MOS transistor on the semiconductor substrate after the LDD is formed.