Semiconductor device and method for manufacturing the same

• US 6,700,144 B2
• Filed: 05/24/2002
• Issued: 03/02/2004
• Est. Priority Date: 05/30/2001
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Shimizu, Yuzo, Ohsawa, Katuichi, Shimazaki, Toyoyuki, Chato, Tetsuo
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US10/155,470
• Publication Number:
  US 20020182801A1
• Time in Patent Office: 648 Days
• Field of Search: 257/430, 257/431, 257/446, 257/458, 257/499, 257/525, 257/565, 257/290, 257/291, 257/292, 257/293, 257/184, 257/187, 438/59, 438/60, 438/73, 438/75, 438/85, 438/144, 438/145, 438/202, 438/234, 438/499, 438/565
• US Class Current: 257/292
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors

Abstract

A semiconductor device includes the following: a semiconductor substrate of a first conduction type; an intrinsic semiconductor layer of the first conduction type formed on the semiconductor substrate; a first semiconductor layer of a second conduction type formed on the intrinsic semiconductor layer; a first impurity layer of the first conduction type formed in the first semiconductor layer of the second conduction type; and a bipolar transistor and a MIS transistor formed in the first semiconductor layer of the second conduction type. The laminated structure of the semiconductor substrate, the intrinsic semiconductor layer, and the first semiconductor layer provides a diode for photoelectric conversion. A first insulator layer and a second insulator layer are formed respectively in at least a portion below the bipolar transistor and the MIS transistor. The transistors are isolated from the semiconductor substrate by the insulator layers, so that the characteristics of the transistors can be adjusted independently of the diode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conduction type;

an intrinsic semiconductor layer of the first conduction type formed on the semiconductor substrate, the intrinsic semiconductor layer having a lower impurity concentration than that of the semiconductor substrate;

a first semiconductor layer of a second conduction type formed on the intrinsic semiconductor layer;

a first impurity layer of the first conduction type formed in the first semiconductor layer of the second conduction type; and

a bipolar transistor and a MIS transistor formed in the first semiconductor layer of the second conduction type,

the laminated structure of the semiconductor substrate, the intrinsic semiconductor layer, and the first semiconductor layer providing a diode for photoelectric conversion,

wherein a first insulator layer is formed in at least a portion below the bipolar transistor and a second insulator layer is formed in at least a portion below the MIS transistor, and

the first insulator layer is formed at a depth deeper than that of the second insulator layer.

2. The semiconductor device according to claim 1, further comprising a third insulator layer that adjoins a lower portion of one of the first insulator layer and the second insulator layer.

3. The semiconductor device according to claim 1, wherein the first insulator layer is formed in a region including the semiconductor substrate and the intrinsic semiconductor layer or only in the intrinsic semiconductor layer.

4. The semiconductor device according to claim 1, wherein the second insulator layer is formed in at least one of the intrinsic semiconductor layer and the first semiconductor layer.

5. The semiconductor device according to claim 1, wherein the first insulator layer is formed in a region including the semiconductor substrate and the intrinsic semiconductor layer or only in the intrinsic semiconductor layer, the second insulator layer is formed in a region including the intrinsic semiconductor layer and the first semiconductor layer or only in the intrinsic semiconductor layer, and the first insulator layer adjoins the second insulator layer.

6. The semiconductor device according to claim 1, wherein at least one of the first insulator layer and the second insulator layer is made of one selected from silicon dioxide and silicon nitride.

7. The semiconductor device according to claim 1, wherein the semiconductor substrate and the intrinsic semiconductor layer are made of silicon.

8. The semiconductor device according to claim 1, wherein the intrinsic semiconductor layer has an impurity concentration of 1×

10¹² atms/cm³ to 1×

10¹³ atms/cm³.

9. The semiconductor device according to claim 1, wherein a thickness of at least one of the first insulator layer and the second insulator layer is larger than a thickness required for electrical insulation.

10. The semiconductor device according to claim 1, wherein the first insulator layer is formed in a boundary portion between the semiconductor substrate and the intrinsic semiconductor layer, and the second insulator layer is formed in a boundary portion between the intrinsic semiconductor layer and the second conduction type layer.

11. A method for manufacturing a semiconductor device comprising:

forming an intrinsic semiconductor layer of a first conduction type on a semiconductor substrate of the first conduction type, the intrinsic semiconductor layer having a lower impurity concentration than that of the semiconductor substrate;

forming a first semiconductor layer of a second conduction type on the intrinsic semiconductor layer;

forming a first impurity layer of the first conduction type in the first semiconductor layer of the second conduction type;

forming a bipolar transistor in a portion of the first semiconductor layer of the second conduction type, the bipolar transistor comprising a collector diffusion layer, a base diffusion layer, and an emitter diffusion layer; and

forming a MIS transistor in a portion of the first semiconductor layer of the second conduction type, the MIS transistor comprising a source diffusion layer and a drain diffusion layer,

the laminated structure of the semiconductor substrate, the intrinsic semiconductor layer, and the first semiconductor layer providing a diode for photoelectric conversion,

wherein a first insulator layer is formed in at least a portion below the bipolar transistor and a second insulator layer is formed in at least a portion below the MIS transistor, and the first insulator layer is formed at a depth deeper than that of the second insulator layer.

12. The method according to claim 11, wherein a third insulator layer is formed so as to adjoin a lower portion of one of the first insulator layer and the second insulator layer.

13. The method according to claim 12, wherein the third insulator layer is formed by a process comprising a third ion implantation and heat treatment at high temperatures.

14. The method according to claim 12, wherein the third insulator layer is formed when forming the first insulator layer or the second insulator layer.

15. The method according to claim 11, wherein the first insulator layer is formed in a region including the semiconductor substrate and the intrinsic semiconductor layer or only in the intrinsic semiconductor layer.

16. The method according to claim 11, wherein the second insulator layer is formed in at least one of the intrinsic semiconductor layer and the first semiconductor layer.

17. The method according to claim 11, wherein the first insulator layer is formed by a process comprising a first ion implantation and heat treatment at high temperatures.

18. The method according to claim 17, wherein the heat treatment at high temperatures causes ions implanted in one of the first ion implantation, the second ion implantation, and the third ion implantation to react with at least one of the semiconductor substrate, the intrinsic semiconductor layer, and the first semiconductor layer.

19. The method according to claim 17, wherein a depth of the first ion implantation is adjusted so that the first insulator layer is formed in at least a portion of a region where the semiconductor substrate and the intrinsic semiconductor layer adjoin one another or only in the intrinsic semiconductor layer.

20. The method according to claim 11, wherein the second insulator layer is formed by a process comprising a second ion implantation and heat treatment at high temperatures.

21. The method according to claim 20, wherein a depth of the second ion implantation is adjusted so that the second insulator layer is formed in at least a portion of a region where the intrinsic semiconductor layer and the first semiconductor layer adjoin one another, only in the intrinsic semiconductor layer, or only in the first semiconductor layer.

22. The method according to claim 11, wherein the first insulator layer is formed in a region including the semiconductor substrate and the intrinsic semiconductor layer or only in the intrinsic semiconductor layer, the second insulator layer is formed in a region including the intrinsic semiconductor layer and the first semiconductor layer or only in the intrinsic semiconductor layer, and the first insulator layer adjoins the second insulator layer.

23. The method according to claim 11, wherein at least one of the first insulator layer and the second insulator layer is made of one selected from silicon dioxide and silicon nitride.

24. The method according to claim 11, wherein the semiconductor substrate and the intrinsic semiconductor layer are made of silicon.

25. The method according to claim 11, wherein the intrinsic semiconductor layer has an impurity concentration of 1×

10¹² atms/cm³ to 1×

10¹³ atms/cm³.

26. The method according to claim 11, wherein a thickness of at least one of the first insulator layer and the second insulator layer is larger than a thickness required for electrical insulation.