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High density parasitic measurement structure

  • US 6,700,399 B1
  • Filed: 12/12/2002
  • Issued: 03/02/2004
  • Est. Priority Date: 12/12/2002
  • Status: Active Grant
First Claim
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1. A partially fabricated wafer having a parasitic capacitance test structure, the test structure comprising:

  • a first structure overlying a substrate and coupled to a first probe pad, the first structure having a first parasitic capacitance relative to the substrate;

    a second structure being located in proximity to the first structure, such that the first structure has a second parasitic capacitance relative to the second structure; and

    a bias circuit having an input coupled to a second probe pad and an output coupled to the second structure, wherein the bias circuit is operable to bias the second structure in response to a select signal impressed on the second probe pad.

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