High density parasitic measurement structure

• US 6,700,399 B1
• Filed: 12/12/2002
• Issued: 03/02/2004
• Est. Priority Date: 12/12/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Savithri, Nagaraj Narasimh
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Nguyen, Trung Q.
• Application Number:
  US10/317,532
• Time in Patent Office: 446 Days
• Field of Search: 324/72.5, 324/754, 324/755, 324/761, 324/762, 324/158.1, 439/219, 439/482, 439/620, 439/103, 439/109, 438/18, 174/207, 257/48
• US Class Current: 324/750.3
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) overlying a substrate of the wafer; biasing a second structure located in proximity to the DUT to have a first electrical state such that a first equivalent test structure is formed; determining a first parasitic parameter associated with the first equivalent test structure by applying a signal to the DUT while the second structure is in the first electrical state and measuring a response that is indicative of the first parameter; biasing the second structure to have a second electrical state such that a second equivalent test structure is formed; and determining a second parasitic parameter associated with the second equivalent test structure by applying a signal to the DUT while the second structure is in the second electrical state and measuring a response that is indicative of the second parameter.

Claims

1. A partially fabricated wafer having a parasitic capacitance test structure, the test structure comprising:

a first structure overlying a substrate and coupled to a first probe pad, the first structure having a first parasitic capacitance relative to the substrate;

a second structure being located in proximity to the first structure, such that the first structure has a second parasitic capacitance relative to the second structure; and

a bias circuit having an input coupled to a second probe pad and an output coupled to the second structure, wherein the bias circuit is operable to bias the second structure in response to a select signal impressed on the second probe pad.

2. The partially fabricated wafer of claim 1, wherein a test signal impressed on the first probe pad is operable to provide a measure of the first parasitic capacitance when the select signal has a first value;

and

the test signal is operable to provide a measure of the second parasitic capacitance when the select signal has a second value.

3. The partially fabricated wafer of claim 2, wherein the first structure is connected to a switching circuit for periodically switching between the first probe pad and the substrate such that a resulting periodic voltage periodically charges and discharges the parasitic capacitance of the first structure, whereby a current drawn through the first probe pad provides a measure of the parasitic capacitance associated with the first structure.

4. The partially fabricated wafer of claim 3, wherein the bias circuit comprises:

a switching circuit with an output connected to the second structure for periodically switching between a third probe pad and the substrate such that a resulting periodic bias voltage periodically charges and discharges the parasitic capacitance of the second structure to a voltage equal to approximately that of the first structure; and

a selection circuit having the input that is coupled to the second probe pad and an output connected to control the switching circuit.

5. The partially fabricated wafer of claim 4, wherein when the select signal has the first value, the switching circuit is directed to bias the second structure with the periodic bias voltage, whereby the test signal provides a measure of the first parasitic capacitance exclusive of the second parasitic capacitance.

6. The partially fabricated wafer of claim 5, wherein when select signal has the second value the switching circuit is directed to bias the second structure with a steady potential, whereby the test signal provides a measure of both the first parasitic capacitance and the second parasitic capacitance.

7. The partially fabricated wafer of claim 6, wherein when select signal has the second value the second structure is biased to have a steady potential equal to approximately that of the substrate.

8. The partially fabricated wafer of claim 1, wherein the parasitic capacitance test structure is located in a scribeline of the wafer.

9. A partially fabricated wafer having a parasitic capacitance test structure, the test structure comprising:

a single reference structure, wherein the reference structure comprises a switching circuit;

a plurality of first structures overlying a substrate each coupled to respective one of a plurality of first probe pads, wherein each of the plurality of first structures comprises a switching circuit connected to a device under test (DUT), wherein a test signal impressed on each of the first probe pads is operable to provide a measure of a parasitic capacitance associated with a respective one of the DUTs; and

wherein the switching circuit of the reference circuit and the switching circuit of each of the first structures all have approximately a same topology and size, whereby the single reference circuit is used to improve the resolution of every one of the plurality of first test structures.

10. The partially fabricated wafer of claim 9, wherein parasitic test structure is located in a scribeline of the wafer.

11. A partially fabricated wafer having a test structure, the test structure comprising:

a first structure coupled to a first probe pad, wherein a test signal impressed on the first probe pad is operable to provide a measure of an operational parameter associated with the first structure;

a second structure coupled to a selection circuit, the second structure being located in proximity to the first structure, such that value of the operational parameter is responsive to a bias signal impressed on the second structure; and

the selection circuit having an input coupled to a second probe pad, wherein the selection circuit is operable to bias the second structure with a selected one of a plurality of bias signals in response to a select signal impressed on the second probe pad, whereby each of a plurality of operational parameter values associated with the first structure can be measured in response to the select signal.

12. The partially fabricated wafer of claim 11, wherein the test structure is located in a scribeline of the wafer.

13. A method for testing a partially fabricated wafer, comprising the steps of:

a) providing a device under test (DUT) overlying a substrate of the wafer and a second structure located in proximity to the DUT;

b) forming a first virtual test structure by biasing the second structure to have a first electrical state;

c) determining a first parasitic parameter associated with the first virtual test structure by applying a signal to the DUT while the second structure is in the first electrical state and measuring a response that is indicative of the first parameter;

d) forming a second virtual test structure by biasing the second structure to have a second electrical state; and

e) determining a second parasitic parameter associated with the second virtual test structure by applying a signal to the DUT while the second structure is in the second electrical state and measuring a response that is indicative of the second parameter.

14. The method of claim 13, wherein step b biases the second structure with a steady voltage and step d biases the second structure with a periodic voltage.

15. The method of claim 13, wherein a plurality of second structures are located in proximity to the DUT, and wherein step b biases all of the plurality of structures to have the first electrical state and step d biases a portion of the plurality of structures to have the first electrical state and a different portion of the plurality of structures to have the second electrical state.

16. A method for testing a partially fabricated wafer using charge based capacitance measurement, comprising the steps of:

applying a first periodic voltage to a device under test (DUT) overlying a substrate in order to periodically charge and discharge the DUT with respect to the substrate;

biasing a second structure located in proximity to the DUT to have a steady voltage;

measuring a current drawn by the DUT while the second structure is biased as a measure of a parasitic capacitance of the DUT with reference to the substrate and to the second structure;

applying a second periodic voltage to the second structure, wherein the second periodic voltage is approximately equal in instantaneous magnitude to the first periodic voltage; and

measuring a current drawn by the DUT while the second periodic voltage is applied to the second structure as a measure of a parasitic capacitance of the DUT with reference to the substrate but not to the second structure.

17. The method of claim 16, further comprising the step of selecting between biasing the second structure with the steady voltage and applying the second periodic voltage to the second structure in response to a select signal.

18. The method of claim 16, wherein the step of applying a first periodic voltage comprises controlling a pseudo inverter circuit to periodically connect the DUT to a first probe pad and then to the substrate, whereby the current drawn by the DUT results from charging and then discharging the DUT.

19. The method of claim 18, further comprising the step of improving the resolution of the current drawn by the DUT by measuring a current drawn by a reference switching circuit that is essentially identical to the first switching circuit but not connected to a DUT.

20. The method of claim 19, wherein a single reference circuit is used to improve the resolution of the current drawn by a plurality DUTs.