Data driver systems with programmable modes

• US 6,700,403 B1
• Filed: 05/15/2002
• Issued: 03/02/2004
• Est. Priority Date: 05/15/2002
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Dillon, Christopher Daniel
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/146,992
• Time in Patent Office: 657 Days
• Field of Search: 326/30, 326/83, 326/86, 326/90, 326/56-58, 327/67, 327/68, 327/108, 330/253, 330/258, 341/156, 341/161-163
• US Class Current: 326/37
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

Data driver systems are provided that have programmable modes of operation to thereby facilitate selection of output signal forms and reduction of output ports in signal conditioning systems (e.g., analog-to-digital converters). The systems effectively reduce pin count by sharing pins between different drivers and selectively configuring the drivers in driver and high output-impedance states.

Claims

1. A programmable driver system that respectively provides first and second output signals at first and second output ports in a rail-to-rail mode and provides low voltage differential signaling (LVDS) output signals at said first and second output ports in an LVDS mode, the system comprising:

first and second inverters respectively coupled to said first and second output ports;

a low voltage differential signaling (LVDS) driver differentially coupled to said first and second output ports; and

a programmable data multiplexer that respectively guides first and second input signals to said first and second inverters and biases said LVDS driver to a high output-impedance state in a rail-to-rail mode and that guides a third input signal to said LVDS driver and biases said first and second inverters to a high output-impedance state in an LVDS mode.

2. The system of claim 1, wherein said first and second inverters are first and second complementary metal-oxide semiconductor (CMOS) inverters.

3. The system of claim 1, wherein:

said LVDS driver includes first, second, third and fourth current-steering switches that are serially-connected to form a circuit bridge with said first and third switches respectively coupled to the top and bottom of a first side of said circuit bridge and said second and fourth switches respectively coupled to the top and bottom of a second side of said circuit bridge; and

said first and second output ports are coupled across said circuit bridge.

4. The system of claim 3, wherein said LVDS driver further includes first and second current sources that are respectively coupled to the top and bottom of said circuit bridge.

5. The system of claim 1, wherein said multiplexer includes:

a first switch network that couples said first inverter to a first input port to receive said first input signal in said rail-to-rail mode and biases said first inverter to a high output-impedance state in said LVDS mode;

a second switch network that couples said second inverter to a second input port to receive said second input signal in said rail-to-rail mode and biases said second inverter to a high output-impedance state in said LVDS mode; and

an LVDS switch network-that differentially couples said LVDS driver to a said third input port to receive said differential input signal in said LVDS mode and biases said LVDS driver to a high output-impedance state in said rail-to-rail mode.

6. The system of claim 5, wherein said LVDS switch network includes:

first and second switch paths between said third input port and said LVDS driver; and

an inverter in said second switch path;

said LVDS driver thereby differentially coupled to said third input port.

7. The system of claim 5, wherein said first input port and said third input port are a common input port.

8. A programmable driver system that provides data output signals at first and second data output ports, the system comprising:

first and second rail-to-rail drivers that are respectively coupled to said first and second data output ports;

a low voltage differential signaling (LVDS) driver that is differentially coupled to said first and second data output ports; and

a programmable data multiplexer that, in a rail-to-rail mode, respectively guides first and second data input signals to said first and second rail-to-rail drivers and biases said LVDS driver in a high output-impedance state and that, in an LVDS mode, differentially guides a third data input signal to said LVDS driver and biases said first and second rail-to-rail drivers in a high output-impedance state.

9. The system of claim 8, wherein said first and second rail-to-rail drivers each include serially-connected first and second transistors.

10. The system of claim 9, wherein:

said first transistor is a p-channel metal-oxide semiconductor (MOS) transistor and said second transistor is an n-channel MOS transistor; and

said data multiplexer couples high and low rail signals respectively to said p-channel and n-channel MOS transistors to bias them in said high output-impedance state.

11. The system of claim 8 wherein:

said LVDS driver includes first, a second, third and fourth current-steering switches that are serially-connected to form a circuit bridge with said first and third switches respectively coupled to the top and bottom of a first side of said circuit bridge and said second and fourth switches respectively coupled to the top and bottom of a second side of said circuit bridge; and

said first and second data output port are coupled across said circuit bridge.

12. The system of claim 8 wherein said multiplexer includes:

a first switch network that couples said first rail-to-rail driver to a first data input port to receive said first data in put signal in said rail-to-rail mode and biases said first rail-to-rail driver to a high output-impedance state in said LVDS mode;

a second switch network that couples said second rail-to-rail driver to a second data input port to receive said second data input signal in said rail-to-rail mode and biases said second rail-to-rail driver to a high output-impedance state in said LVDS mode; and

an LVDS switch network that differentially couples said LVDS driver to an LVDS data input port to receive said third data input signal in said LVDS mode and biases said LVDS driver to a high output-impedance state in said rail-to-rail mode.

13. The system of claim 11, wherein said LVDS switch network includes:

first and second switch paths between said third data input port and said LVDS driver; and

an inverter in said second switch path;

said LVDS driver thereby differentially coupled to said LVDS data input port.

14. The system of claim 11, wherein said first data input port and said third data input port are a common data input port.

15. An analog-to-digital converter (ADC) system that provides selectable rail-to-rail output signals and LVDS output signals at ADC output ports, the system comprising:

an ADC that converts analog input signals into digital output signals; and

a programmable driver system that includes;

a) pairs of rail-to-rail drivers wherein each of said drivers is coupled to a respective one of said ADC output ports;

b) low voltage differential signaling (LVDS) drivers that are each differentially coupled to a respective pair of said ADC output ports; and

c) a programmable multiplexer that, in a rail-to-rail mode, respectively guides each of said digital output signals to a respective one of said first and second rail-to-rail drivers and biases each of said LVDS drivers in a high output-impedance state and that, in an LVDS mode, differentially guides each of said digital output signals to a respective one of said LVDS drivers and biases each of said rail-to-rail drivers in a high output-impedance state.

16. The system of claim 15, wherein said ADC is a successive approximation ADC.

17. The system of claim 15, wherein said ADC is a flash ADC.

18. The system of claim 15, wherein said ADC is a pipelined ADC.

19. The system of claim 15, wherein said rail-to-rail drivers each include serially-connected first and second transistors.

20. The system of claim 19, wherein:

said first transistor is a p-channel metal-oxide semiconductor (MOS) transistor and said second transistor is an n-channel MOS transistor; and

said multiplexer couples high and low rail signals respectively to said p-channel and n-channel MOS transistors to bias them in said high output-impedance state.

21. The system of claim 15, wherein:

each of said LVDS drivers includes first, second, third and fourth current-steering switches that are serially-connected to form a circuit bridge with said first and third switches respectively coupled to the top and bottom of a first side of said circuit bridge and said second and fourth switches respectively coupled to the top and bottom of a second side of said circuit bridge; and

said first and second sides of said circuit bridge are coupled across said respective pair of ADC output ports.

22. The system of claim 15, wherein said multiplexer includes:

rail-to-rail switch networks that each guides a respective one of said digital output signals to a respective one of said rail-to-rail drivers in said rail-to-rail mode and biases each of said rail-to-rail drivers to a high output-impedance state in said LVDS mode; and

LVDS switch networks that each differentially couples a respective one of said digital output signals to a respective one of said LVDS drivers in said LVDS mode and biases each of said LVDS drivers to a high output-impedance state in said rail-to-rail mode.

23. The system of claim 22, wherein each of said LVDS switch networks includes:

first and second switch paths that are coupled to the respective LVDS driver; and

an inverter in said second switch path;

the respective digital output signal thereby differentially coupled to the respective LVDS driver.