Signal settling device and method

• US 6,700,522 B2
• Filed: 05/23/2002
• Issued: 03/02/2004
• Est. Priority Date: 02/15/2001
• Status: Active Grant

• Current Assignee: Iowa Lottery Authority, Multi-State Lottery Association, Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Huckins, Kevin, Ivanov, Vadim V.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Linh V
• Application Number:
  US10/154,165
• Publication Number:
  US 20030218482A1
• Time in Patent Office: 649 Days
• Field of Search: 341/118, 341/120, 341/122, 341/144, 341/155, 341/143, 330/9, 330/107, 330/109, 330/924, 330/126, 330/151
• US Class Current: 341/155
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2203/30084 the pull circuit of the SEPP amplifier being a cascode circuit
• CPC Class Codes: H03F 2203/30096 An op amp being used as extra drive amp for the pull side of the SEPP
• CPC Class Codes: H03F 2203/30117 the push circuit of the SEPP amplifier being a cascode circuit
• CPC Class Codes: H03F 2203/30129 An op amp being used as extra drive amp for the push side of the SEPP
• CPC Class Codes: H03F 2203/30151 the current sink of the push driven, i.e. source driven SEPP amplifier being a cascode current mirror
• CPC Class Codes: H03F 2203/30156 the current source of the pull driven, i.e. sink driven SEPP amplifier being a cascode current mirror
• CPC Class Codes: H03F 3/3028 with symmetrical driving of the end stage
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45269 Complementary non-cross coupled types
• CPC Class Codes: H03F 3/45273 Mirror types
• CPC Class Codes: H03F 3/45291 Folded cascode stages
• CPC Class Codes: H03F 3/45367 Complementary non-cross coupled types
• CPC Class Codes: H03F 3/45372 Mirror types
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence

Abstract

A method and device are configured for providing for both quick and accurate signal settling. A high accuracy component is configured in parallel with a high speed component. The high accuracy component may be an op-amp. The high speed component may be an OTA that is configured to be a non-linear OTA. Furthermore, an ADC is configured to internally provide both quick and accurate signal settling. For example, an ADC comprises an internal high speed OTA configured in parallel with a connected external op-amp. The OTA is configured to be a non-linear OTA.

Claims

1. An input signal settling system for use in an analog to digital converter (“

ADC”

) system, the input signal settling system comprising;

an ADC comprising an ADC input port;

a high accuracy component configured to settle a first input signal with high accuracy and to communicate said high accuracy settled signal to said ADC input port;

a resistor configured between an output of said high accuracy component and said ADC input port; and

a high speed component configured to settle said first input signal with high speed and in parallel with said high accuracy component and to communicate said high speed settled signal to said ADC input port.

2. The input signal settling system of claim 1 wherein said high accuracy component is an op-amp.

3. The input signal settling system of claim 1 wherein said high speed component is an OTA.

4. The input signal settling system of claim 3, wherein said OTA comprises a differential input stage configured to divide a constant current flow between two control lines to each of two current mirrors.

5. The input signal settling system of claim 3, wherein said OTA comprises an upper current mirror and a lower current mirror, and wherein said current mirrors are configured such that said OTA has a high output impedance.

6. The input signal settling system of claim 3 wherein said ADC comprises said OTA.

7. The input signal settling system of claim 3 wherein said OTA is external to said ADC.

8. The input signal settling system of claim 3 wherein said OTA is configured to be non-linear.

9. The input signal settling system of claim 8 wherein said OTA further comprises a slew boost stage.

10. The input signal settling system of claim 8 wherein said OTA is configured to cause an output current from said non-linear OTA to be strongest when said OTA should dominate the signal settling process, and is weakest when a high accuracy op-amp should dominate the signal settling process.

11. The input signal settling system of claim 1 wherein said high speed component is further configured to settle said first input signal to within less than 100 milli-volts of a true voltage level within less than 500 nanoseconds.

12. The input signal settling system of claim 11 wherein said high accuracy component is configured to further settle said first input signal to within less than 300 micro-volts of a true voltage level within less than 800 nanoseconds.

13. The input signal settling system of claim 1 wherein said high speed component and said high accuracy component are further configured to settle said first input signal to within less than 300 micro-volts of a true voltage level within less than 400 nanoseconds.

14. The input signal settling system of claim 1 wherein said high speed component and said high accuracy component are further configured such that said output voltage is accurate to within 0.0015% of the full scale voltage range within less than 500 nanoseconds.

15. An input signal settling system for use in an analog to digital converter (“

ADC”

) system, the input signal settling system comprising;

an ADC comprising an ADC input port;

an op-amp configured to settle a first input signal with high accuracy and to communicate said high accuracy settled signal to said ADC input port;

a resistor configured between an output of said op-amp and said ADC input port; and

an OTA configured to settle said first input signal with high speed and in parallel with said op-amp and to communicate said high speed settled signal to said ADC input port.