A/D converter for performing pipeline processing

• US 6,700,524 B2
• Filed: 09/27/2002
• Issued: 03/02/2004
• Est. Priority Date: 09/27/2001
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Okamoto, Yoichi, Oka, Koji, Inagaki, Yoshitsugu, Naka, Junichi, Murata, Kenji
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/256,238
• Publication Number:
  US 20030058150A1
• Time in Patent Office: 522 Days
• Field of Search: 341/155, 341/120, 341/161
• US Class Current: 341/161
• CPC Class Codes: H03M 1/007 among different resolutions
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

An A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter, which is requested by the system, is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, a breakdown of an output from the A/D converter is avoided.

Claims

1. An A/D converter comprising:

a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage for performing a pipeline operation on an inputted analog voltage to output a digital voltage;

a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and

a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal.

2. An A/D converter as defined in claim 1, wherein said correction circuit comprises:

a correction A/D converter for receiving inputs of all of the pipeline stages, comparing an input that is selected from the inputs according to the number-of-bits selection signal, with a reference voltage value, and outputting a result of comparison as a first partial digital value for correction which comprises at least one binary code; and

a correction code conversion circuit for receiving second partial digital values which are outputted from all of the pipeline stages in the pipeline stage array, and the first partial digital value for correction which is outputted from the correction A/D converter, and outputting at least one binary code according to the number-of-bits selection signal.

3. An A/D converter as defined in claim 1, wherein said correction circuit comprises:

a selection means for selecting an analog voltage value to be processed in a final pipeline stage, from among analog voltage values which are outputted from the plural pipeline stages except the final pipeline stage, according to the number-of-bits selection signal; and

a correction code conversion circuit for receiving a partial digital value outputted from the final pipeline stage, and partial digital values outputted from the respective pipeline stages in the pipeline stage array other than the final pipeline stage, and outputting corrected binary codes according to the number-of-bits selection signal.

4. An A/D converter as defined in claim 1, wherein said correction circuit comprises:

an offset control means for determining whether offset addition should be performed in the plural pipeline stages except the final pipeline stage, according to the number-of-bits control signal, and controlling the plural pipeline stages to output corrected binary codes.