Sense amplifier bias circuit for a memory having at least two distinct resistance states

• US 6,700,814 B1
• Filed: 10/30/2002
• Issued: 03/02/2004
• Est. Priority Date: 10/30/2002
• Status: Expired due to Term

• Current Assignee: VLSI Technology LLC (SoftBank Group Corp.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Garni, Bradley J., Andre, Thomas W., Nahas, Joseph J.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US10/283,622
• Time in Patent Office: 489 Days
• Field of Search: 365/158, 365/205, 365/207, 365/209, 365/210
• US Class Current: 365/158
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

In a memory, a bias circuit (112, 212, 312, 412) uses a current reference (108) for providing a reference current and control circuitry (106, 120) to bias a sense amplifier (114) with a varying voltage (V_B). The varying voltage maintains current through MRAM bit cells (177-179) at a value proportional to the reference current over variations in average bit cell resistance with immunity to variations in process, supply voltage and temperature. In one form, a mock sense amplifier (122, 126, 132, 134) and mock array of bit cells (130, 136) are used to establish internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs and to generate the varying bias voltage. Matching diode-connected transistors in each of the control circuitry and either the mock sense amplifier or the sense amplifier is used to generate the varying bias voltage.

Claims

1. A sense amplifier bias circuit for a memory having a sense amplifier and an array of bit cells, each of the bit cells having at least two distinct resistance states, comprising:

a mock sense amplifier and mock array of bit cells that when biased establishes internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs;

a current reference for providing a reference current; and

control circuitry coupled to the current reference, the mock sense amplifier and mock array of bit cells, the control circuitry biasing the mock sense amplifier and mock array of bit cells to maintain current through the bit cells in the mock array of bit cells at a value proportional to the reference current over variations in average bit cell resistance.

2. The sense amplifier bias circuit of claim 1 wherein the control circuitry further comprises:

a diode-connected transistor that matches one or more transistors in the mock sense amplifier to create a varying voltage that when used to bias one of the one or more transistors in the mock sense amplifier functions to maintain a current proportional to the reference current through the bit cells in the mock array of bit cells.

3. The sense amplifier bias circuit of claim 2 wherein the diode-connected transistor further matches one or more transistors in the sense amplifier.

4. The sense amplifier bias circuit of claim 2 wherein the control circuitry further comprises:

an operational amplifier having a first input connected to the diode-connected transistor for receiving the varying voltage, a second input connected to the mock sense amplifier for receiving a comparison voltage established within the mock sense amplifier to track the varying voltage, and an output for providing an output bias voltage for biasing the sense amplifier.

5. The sense amplifier bias circuit of claim 1 wherein the control circuitry further comprises:

a first transistor of a first conductivity type having a first current electrode connected to a first supply voltage terminal, and a second current electrode and a control electrode connected together; and

an operational amplifier having a first input connected to the second current electrode of the first transistor, a second input and an output; and

the mock sense amplifier comprises;

a second transistor of the first conductivity type having a first current electrode connected to the first supply voltage terminal, and a second current electrode and a control electrode connected together and to the second input of the operational amplifier;

a third transistor of a second conductivity type having a first current electrode connected to the second current electrode of the second transistor, a control electrode connected to the output of the operational amplifier, and a second current electrode;

a fourth transistor of the first conductivity type having a first current electrode connected to the first supply voltage terminal, and a second current electrode and a control electrode connected together and to the second input of the operational amplifier;

a fifth transistor of the second conductivity type having a first current electrode connected to the second current electrode of the fourth transistor, a control electrode connected to the output of the operational amplifier, and a second current electrode; and

the mock array of bit cells comprise;

a first bit cell coupled between the second current electrode of the third transistor and a second supply voltage terminal, the first bit cell being programmed in a high resistance value; and

a second bit cell coupled between the second current electrode of the fifth transistor and the second supply voltage terminal, the second bit cell being programmed in a low resistance value.

6. The sense amplifier bias circuit of claim 1 wherein the control circuitry further comprises:

a first transistor of a first conductivity type having a first current electrode connected to a first supply voltage terminal, and a second current electrode and a control electrode connected together; and

an operational amplifier having a first input connected to the second current electrode of the first transistor, and a second input and an output connected together; and

the mock sense amplifier comprises;

a second transistor of the first conductivity type having a first current electrode connected to the first supply voltage terminal, a control electrode connected to the output of the operational amplifier, and a second current electrode;

a third transistor of a second conductivity type having a first current electrode connected to the second current electrode of the second transistor and to a control electrode thereof and having a second current electrode;

a fourth transistor of the first conductivity type having a first current electrode connected to the first supply voltage terminal, a control electrode connected to the output of the operational amplifier, and a second current electrode;

a fifth transistor of the second conductivity type having a first current electrode connected to both the second current electrode of the fourth transistor and the first current electrode of the third transistor, a control electrode connected to the control electrode of the third transistor, and a second current electrode; and

the mock array of bit cells comprise;

a first bit cell coupled between the second current electrode of the third transistor and a second supply voltage terminal, the first bit cell being programmed in a high resistance value; and

a second bit cell coupled between the second current electrode of the fifth transistor and the second supply voltage terminal, the second bit cell being programmed in a low resistance value.

7. A sense amplifier bias circuit for a memory having a sense amplifier and an array of bit cells, each of the bit cells having at least two distinct resistance states, comprising:

a current reference for providing a reference current; and

control circuitry coupled to the current reference and the sense amplifier, the control circuitry using a diode-connected transistor that matches a transistor in the sense amplifier to create a varying bias voltage, the varying bias voltage maintaining current through a plurality of bit cells in an array of bit cells at a value proportional to the reference current over variations in average bit cell resistance.

8. The sense amplifier bias circuit of claim 7 wherein the control circuitry further comprises:

an operational amplifier coupled to the current reference and to the sense amplifier, the operational amplifier providing the varying bias voltage by using either a current or a voltage established within the sense amplifier during operation as feedback to control how the varying bias voltage is varied.

9. A sense amplifier bias circuit for a memory having a sense amplifier and an array of bit cells, each of the bit cells having at least two distinct resistance states, comprising:

means for simulating circuit conditions in the sense amplifier and array of bit cells so that when the means for simulating circuit conditions are biased, the means for simulating circuit conditions establishes internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs;

current reference means for providing a reference current; and

control means coupled to the current reference means and the means for simulating circuit conditions, the control means biasing the means for simulating circuit conditions to maintain current through the array of bit cells at a value proportional to the reference current over variations in average bit cell resistance.

10. The sense amplifier bias circuit of claim 9 wherein the control means further comprise a diode-connected transistor for establishing a varying bias voltage for use by the sense amplifier to maintain current through the array of bit cells at the value that is proportional to the reference current.

11. A memory having a sense amplifier bias circuit, the memory comprising:

a first transistor that is connected to a power supply voltage terminal and is diode-connected by having a control electrode connected to a current electrode thereof;

a current source connected in series with the first transistor between the first transistor and a reference terrninal, the current source providing a reference current;

an operational amplifier having a first input connected to the current source and first transistor, a second input, and an output;

a sense amplifier having a second transistor that is diode-connected and which establishes a voltage or current that is used as a feedback signal that is connected to the second input of the operational amplifier, the sense amplifier being biased by a variable bias voltage provided by the output of the operational amplifier; and

an array of memory bit cells coupled to the sense amplifier, the variable bias voltage maintaining current through the array of memory bit cells at a value proportional to the reference current over variations in average bit cell resistance.

12. The memory of claim 11 wherein the array of memory bit cells further comprise:

bit cells, each having at least two distinct resistance states to indicate how each is programmed.

13. The memory of claim 11 wherein the memory is a magnetoresistive random access memory (MRAM).

14. A memory having a sense amplifier bias circuit, the memory comprising:

a first transistor that is connected to a power supply voltage terminal and is diode-connected by having a control electrode connected to a current electrode thereof;

a current source connected in series with the first transistor between the first transistor and a reference terminal, the current source providing a reference current;

an operational amplifier having a first input connected to the current source and first transistor, a second input, and an output;

a sense amplifier having a second transistor with a control electrode coupled to the output of the operational amplifier, the second transistor establishing a bias current in the sense amplifier that is proportional to the reference current; and

an array of memory bit cells coupled to the sense amplifier.

15. The memory of claim 14 wherein the array of memory bit cells further comprise:

bit cells, each having at least two distinct resistance states to indicate how each is programmed.

16. The memory of claim 14 wherein the memory is a magnetoresistive random access memory (MRAM).