High speed cross point switch routing circuit with word-synchronous serial back plane

• US 6,700,886 B2
• Filed: 01/14/2002
• Issued: 03/02/2004
• Est. Priority Date: 08/05/1998
• Status: Expired due to Term

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: Vitesse Semiconductor Corp (Microchip Technology Incorporated)
• Inventors: Lee, Gary M., Mullaney, John P.
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US10/047,166
• Publication Number:
  US 20020061016A1
• Time in Patent Office: 778 Days
• Field of Search: 370/360, 370/365, 370/367, 370/226, 370/228, 370/427, 370/509-514
• US Class Current: 370/365
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5674 Synchronisation, timing recovery or alignment
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 2012/5684 Characteristics of traffic flows
• CPC Class Codes: H04L 49/1576 Crossbar or matrix
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

Claims

1. A high speed network switching system comprising a switch including a plurality of pairs of switch transmit and receive ports, each of the pairs of switch transmit and receive ports coupled to a corresponding one of a plurality of transceivers, the transceivers adapted to transmit serial data formed in data words, the data words comprising overhead bits and payload, to the switch receive ports and to receive serial data formed in data words from the switch transmit ports, the switch including:

a switch fabric reconfigurably interconnecting the switch transmit and receive ports such that the switch fabric provides a switch transmit port of a first pair of switch transmit and receive ports with payload from a switch receive port of a second pair of switch transmit and receive ports and the switch fabric provides the switch transmit port of a third pair of switch transmit and receive ports with payload from switch receive port of the first pair of switch transmit and receive ports;

a reverse switch fabric reconfigurably interconnecting the switch transmit and receive ports such that the switch fabric provides the switch transmit port of the first pair of switch transmit and receive ports with overhead bits from the switch receive port of the third pair of switch transmit and receive ports and the switch fabric provides the switch transmit port of the second pair of switch transmit and receive ports with overhead bits from the switch receive port of the first pair of switch transmit and receive ports; and

a means for routing the payload to the switch fabric and means for routing the overhead bits to the reverse switch fabric.

2. The high speed network switching system of claim 1 wherein the overhead bits transmitted by a particular transceiver indicate that the particular transceiver is able to receive data when the overhead bits are configured in a first pattern.

3. The high speed network switching system of claim 1 wherein the overhead bits transmitted by a particular switch transmit port to a particular transceiver indicate acknowledgment of receipt by the particular switch receive port of a request by the particular transceiver.

4. The high speed network switching system of claim 1 wherein the overhead bits transmitted by a particular switch transmit port to a particular transceiver indicate the granting of a connection request requested by the particular transceiver.