Method, system and apparatus for initiating and maintaining synchronization of a pulse position modulation (PPM) decoder with a received PPM signal

• US 6,700,931 B1
• Filed: 07/06/2000
• Issued: 03/02/2004
• Est. Priority Date: 07/06/2000
• Status: Active Grant

• Current Assignee: CHECKPOINT SYSTEMS, INC. (CCL Industries Incorporated), Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Gallagher, William F., Inui, Shinichiro, Alexander, Sam, Lee, Youbok, Salesky, Ron, Furey, Lee
• Primary Examiner(s): Vo, Don N.
• Assistant Examiner(s): Ghulamali, Qutbuddin
• Application Number:
  US09/611,104
• Time in Patent Office: 1,335 Days
• Field of Search: 375/239, 375/240.02, 375/240.28, 329/313
• US Class Current: 375/239
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation

Abstract

A radio frequency identification (RFID) tag device having a pulse position modulation (PPM) decoder circuit which calculates a relative frequency relationship between an internal clock-oscillator of the RFID tag device and an external PPM source such as a RFID tag reader, and then synchronizes the RFID tag device PPM decoder circuit to the required precision for reliable PPM symbol decoding. The PPM decoder is synchronized by measuring the “counts per pulse” (CPP) from a calibration cycle having a plurality of pulses in a single symbol frame.

Claims

1. An apparatus for initiating and maintaining synchronization of a pulse position modulation (PPM) decoder with a received PPM signal, comprising:

a bit counter comprising a modulo-n counter having data inputs, a clock input, a reset input and a Q output, and a carry flip-flop having a data input, a clock input, a reset input and a Q-not output; and

a bit window counter comprising a modulo-p counter having a clock input, a set input and a plurality of outputs;

wherein

the data inputs of the modulo-n counter are adapted to receive a reload value from a calibration/reload function,

the clock input of the modulo-n counter is adapted to receive an internal oscillator clock signal,

the Q output of the modulo-n counter is connected to the clock input of the carry flipflop,

the Q-not output of the carry flipflop is connected to the data input of the carry flipflop and the clock input of the modulo-p counter,

the reset inputs of the modulo-n counter and the carry flipflop are adapted to resynch the modulo-n counter and the carry flipflop at a rising edge of a PPM pulse, and

the set input of the modulo-p counter is adapted to set the modulo-p counter at a rising edge of a last pulse of a calibration symbol.

2. The apparatus according to claim 1, wherein the bit window counter is a modulo-16 counter having a four bit output representing a pulse position in a PPM data symbol.

3. The apparatus according to claim 1, wherein the modulo-n counter counts off two half periods of the PPM pulse, and at each of the two half periods the Q output of the modulo-n counter toggles the carry flipflop.

4. The apparatus according to claim 1, wherein the reload value puts a count value into the modulo-n counter at about a midpoint of the PPM pulse relative to a frequency of an internal oscillator so that a rising edge of the not-Q output of the carry flipflop clocks the modulo-p counter which thereby tracks a pulse position count of a PPM data symbol.

5. The apparatus according to claim 4, wherein the modulo-p counter is a modulo 16 counter having a four bit output and the PPM data symbol is a 1 of 16 PPM data symbol.

6. The apparatus according to claim 1, wherein the internal oscillator is an integer multiple of the PPM pulse frequency.

7. The apparatus according to claim 1, wherein the bit counter is a down-counter.

8. The apparatus according to claim 1, wherein the bit counter is an up-counter.

9. The apparatus according to claim 1, wherein the bit counter is a gray code counter.

10. The apparatus according to claim 1, wherein the calibration symbol is represented by a calibration sequence of three pulses at symbol pulse positions 0, 6 and 14.

11. A pulse position modulation (PPM) decoder, comprising:

a synchronizer adapted to receive a detected PPM modulation;

a PPM decoder state machine connected to the synchronizer;

a calibration-reload function connected to the PPM decoder state machine;

an internal oscillator;

a symbol register;

a bit counter connected to the calibration reload function, the bit counter comprising a modulo-n counter having data inputs, a clock input, a reset input and a Q output, and a carry flipflop having a data input, a clock input, a reset input and a Q-not output;

a bit window counter connected to the bit counter, the bit widow counter comprising a modulo-p counter having a clock input, a set input and a plurality of outputs;

wherein

the data inputs of the modulo-n counter receives a reload value from the calibration/reload function,

the clock input of the modulo-n counter is connected to the internal oscillator,

the Q output of the modulo-n counter is connected to the clock input of the carry flipflop,

the Q-not output of the carry flipflop is connected to the data input of the carry flipflop and the clock input of the modulo-p counter,

the reset inputs of the modulo-n counter and the carry flipflop are adapted to resynch the modulo-n counter and the carry flipflop at a rising edge of a PPM pulse, and

the set input of the modulo-p counter is adapted to set the modulo-p counter at a rising edge of a last pulse of a calibration symbol; and

the internal oscillator is connected to the synchronizer, the PPM decoder state machine, the calibration-reload function and the bit counter.

12. The PPM decoder according to claim 11, wherein the internal oscillator frequency is an integer multiple of the PPM pulse frequency.

13. The PPM decoder according to claim 11, wherein the bit counter is a down-counter.

14. The PPM decoder according to claim 11, wherein the bit counter is an up-counter.

15. The PPM decoder according to claim 11, wherein the bit counter is a gray code counter.

16. The PPM decoder according to claim 11, wherein the calibration symbol is represented by a calibration sequence of three pulses at symbol pulse positions 0, 6 and 14.

17. The PPM decoder according to claim 11, further comprising an integrated circuit RFID tag device having the PPM decoder.

18. The PPM decoder according to claim 17, further comprising a radio frequency system having an RFID tag reader and the integrated circuit RFID tag device having the PPM decoder.

19. A method for initiating and maintaining synchronization of a pulse position modulation (PPM) decoder with a received PPM signal, said method comprising the steps of:

resetting a modulo-n countermand a carry flipflop on a rising edge of a PPM pulse;

loading a reload value into the modulo-n counter;

clocking the modulo-n counter with an internal oscillator;

clocking the carry flipflop with an output from the modulo-n counter wherein the carry flipflop output toggles for each clock pulse from the modulo-n counter;

setting a modulo-p counter with a rising edge of a last pulse of a calibration symbol; and

tracking a pulse position of a 1 of P PPM data symbol by clocking the modulo-p counter with an output of the carry flipflop.

20. The method of claim 19, wherein the step of resetting the modulo-n counter comprises the steps of:

determining a first logic value of the carry flipflop output at a previous internal clock pulse and a second logic value of the carry flipflop output at a present internal clock pulse;

if the first and second logic values are the same do nothing, and

if the first and second logic values are different then increment a value in the modulo-p counter.

21. The method of claim 19, wherein the step of tracking the pulse position of the 1 of P PPM data symbol comprises the steps of:

sampling the modulo-p counter for the pulse position of the received 1 of P PPM data symbol; and

resynchronizing the modulo-p counter to the next received 1 of P PPM data symbol.

22. The method of claim 19, wherein P is 16 and the modulo-p counter is a modulo-16 counter.

23. The method of claim 19, wherein the calibration symbol is represented by a calibration sequence of three pulses at symbol pulse positions 0, 6 and 14.