Method for reliability testing leakage characteristics in an electronic circuit and a testing device for accomplishing the source

• US 6,701,270 B1
• Filed: 09/20/2001
• Issued: 03/02/2004
• Est. Priority Date: 09/20/2001
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Govind, Anand, Miller, Leah M.
• Primary Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US09/957,410
• Time in Patent Office: 894 Days
• Field of Search: 324/500, 324/512, 324/327, 324/537, 324/754, 324/761, 702/117, 702/118, 702/120, 714/1, 714/25, 714/724, 714/734
• US Class Current: 702/117
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

The present invention provides a method for reliability testing leakage characteristics in an electronic circuit, and a testing device for accomplishing the same. In an advantageous embodiment, the method includes dividing conductors of an electronic circuit into at least first and second noninterleaved regions having at least two conductors each. The method further includes forming conductor nets by electrically connecting ones of the at least two conductors of the first region to ones of the at least two conductors of the second region then testing for electrical leakage in the conductor nets.

Claims

1. A method for reliability testing leakage characteristics in an electronic circuit, comprising:

dividing conductors of an electronic circuit into at least first and second noninterleaved regions having at least two conductors each;

forming conductor nets by electrically connecting ones of the at least two conductors of the first region to ones of the at least two conductors of the second region; and

testing for electrical leakage in the conductor nets.

2. The method as recited in claim 1 wherein the ones of the at least two conductors of the first region are symmetric to the ones of the at least two conductors of the second region.

3. The method as recited in claim 1 further including biasing adjacent conductor nets with differing voltages prior to testing for electrical leakage.

4. The method as recited in claim 1 wherein the conductors are signal conductors and further including dividing voltage conductors of the electronic circuit and ground conductors of the electronic circuit, respectively, into the at least first and second noninterleaved regions, and electrically connecting the voltage conductors to form voltage conductor nets and electrically connecting the ground conductors to form ground conductors nets.

5. The method as recited in claim 4 wherein testing for electrical leakage includes testing for electrical leakage using a pin tester having $\left(\frac{N}{P}\right)+V$

pins, wherein N is a number of signal conductors, P is a number of noninterleaved regions and V is a number of voltage conductor nets and ground conductor nets.

6. The method as recited in claim 1 wherein the at least first and second noninterleaved regions include at least four conductors each, and further including daisy chaining sets of adjacent conductors within the regions at a die level, and wherein the ones are the sets of adjacent conductors.

7. The method as recited in claim 6 further including biasing adjacent conductor nets with differing voltages prior to testing for electrical leakage.

8. The method as recited in claim 6 wherein the conductors are signal conductors and further including dividing voltage conductors of the electronic circuit and ground conductors of the electronic circuit, respectively, into the at least first and second noninterleaved regions, and electrically connecting the voltage conductors to form voltage conductor nets and electrically connecting the ground conductors to form ground conductors nets.

9. The method as recited in claim 8 wherein testing for electrical leakage includes testing for electrical leakage using a pin tester having $(\frac{N}{P}$

 



M)+V

pins, wherein N is a number of signal conductors, P is a number of noninterleaved regions, M is a number of adjacent conductors in the daisy chained sets, and V is a number of voltage conductor nets and ground conductor nets.

10. The method as recited in claim 1 wherein dividing conductors of an electronic circuit into at least first and second noninterleaved regions includes dividing conductors of an electronic circuit into up to about 9 noninterleaved regions.

11. A testing device for reliability testing leakage characteristics in an electronic circuit, comprising:

a reliability test board having at least two reliability test board conductors configured to contact and divide an electronic circuit having conductors into at least first and second noninterleaved regions having at least two conductors each, and form conductor nets by electrically connecting ones of the at least two conductors of the first region to ones of the at least two conductors of the second region; and

testing circuitry, coupled to the reliability test board, that tests for electrical leakage in the conductor nets.

12. The testing device as recited in claim 11 wherein the ones of the at least two conductors of the first region are symmetric to the ones of the at least two conductors of the second region.

13. The testing device as recited in claim 11 further including biasing circuitry, coupled to the reliability test board, that biases adjacent conductor nets with differing voltages prior to testing for electrical leakage.

14. The testing device as recited in claim 11 wherein the conductors are signal conductors and further including voltage conductors and ground conductors that are divided into the at least first and second noninterleaved regions, wherein the voltage conductors and ground conductors are electrically connected, respectively, to form voltage conductor nets and ground conductor nets.

15. The testing device as recited in claim 14 wherein the testing circuitry includes a pin tester having $\left(\frac{N}{P}\right)+V$

pins, wherein N is a number of signal conductors, P is a number of noninterleaved regions and V is a number of ground conductor nets and voltage conductor nets.

16. The testing device as recited in claim 11 wherein the at least first and second noninterleaved regions include at least four conductors each, and further including daisy chained sets of adjacent conductors within the regions at a die level, and wherein the ones are the sets of adjacent conductors.

17. The testing device as recited in claim 16 wherein the conductors are signal conductors and further including voltage conductors and ground conductors that are divided into the at least first and second noninterleaved regions, wherein the voltage conductors and ground conductors are connected, respectively, to form voltage conductor nets and ground conductor nets.

18. The testing device as recited in claim 17 wherein the testing circuitry includes a pin tester having $(\frac{N}{P}$

 



M)+V

pins, wherein N is a number of signal conductors, P is a number of noninterleaved regions, M is a number of adjacent conductors in the daisy chained sets, and V is a number of ground conductor nets and voltage conductor nets.

19. The testing device as recited in claim 11 wherein the electronic circuit has up to about 9 noninterleaved regions.

20. The testing device as recited in claim 11 wherein the electronic circuit comprises a semiconductor device and the conductors are traces included in the semiconductor device.