Double differential comparator and programmable analog block architecture using same

• US 6,701,340 B1
• Filed: 09/22/2000
• Issued: 03/02/2004
• Est. Priority Date: 09/22/1999
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Gorecki, James L., Yang, Yaohua, Gazeley, Bill G.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/668,896
• Time in Patent Office: 1,257 Days
• Field of Search: 708/801, 708/1-9, 708/671, 340/146.2
• US Class Current: 708/801
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: H03H 11/04 Frequency selective two-port networks
• CPC Class Codes: H03K 5/249 using clock signals

Abstract

A double differential comparator can be efficiently implemented utilizing a first comparator stage having a folded cascode with floating gate input terminals and clamped single-ended output, and a capacitively coupled input stage for transferring a weighted sum of input signals to the floating gates of the first comparator stage. Additionally, the double differential comparator can be integrated into fully differential programmable analog integrated circuits. Such fully differential programmable analog integrated circuits can also include a differential output digital-to-analog converter to be used with or without the double differential comparator.

Claims

1. A programmable analog integrated circuit for receiving a differential analog input signal and providing a processed differential analog output signal, the programmable analog circuit comprising:

a first programmable analog circuit block, the first programmable analog circuit block having first analog circuit block positive and negative input terminals and first analog circuit block positive and negative output terminals;

a double differential comparator, the double differential comparator including;

first comparator positive and negative input terminals;

second comparator positive and negative input terminals; and

comparator positive and negative output terminals, the double differential comparator providing a logic high output signal at the comparator output terminals when a first differential voltage applied to the first comparator input terminals is positive with respect to a second differential voltage applied to the second comparator input terminals; and

an analog routing pool, the analog routing pool controlling the routing of the differential analog input signal and signals provided by and to the first programmable analog circuit block and the double differential comparator, the analog routing pool being programmable.

2. The programmable analog integrated circuit of claim 1 further comprising:

a memory coupled to the analog routing pool, the memory storing information for use in programming the analog routing pool.

3. The programmable analog integrated circuit of claim 2, wherein the memory is a nonvolatile memory.

4. The programmable analog integrated circuit of claim 1 further comprising:

a second programmable analog circuit block, the second programmable analog circuit block having second analog circuit block positive and negative input terminals and second analog circuit block positive and negative output terminals.

5. The programmable analog integrated circuit of claim 1, wherein the first programmable analog circuit block further comprises:

a first input transconductor, the input transconductor having a programmable transconductance, the input transconductor having an input transconductor positive input terminal and an input transconductor negative input terminal coupled to receive the differential analog input signal and an input transconductor positive output terminal and an input transconductor negative output terminal;

an amplifier, the amplifier including first and second amplifier input terminals and first and second amplifier output terminals, the positive and negative input transconductor output terminals being coupled to the first and second amplifier input terminals, the amplifier output terminals being coupled to the first and second amplifier input terminals, the amplifier output terminals providing the processed differential analog output signal; and

a feedback transconductor, the feedback transconductor including a feedback transconductor positive input terminal and a feedback transconductor negative input terminal and a feedback transconductor positive output terminal and a feedback transconductor negative output terminal, the feedback transconductor positive and negative input terminals being coupled to the first and second amplifier output terminals and the feedback transconductor positive and negative output terminals being coupled to the first and second amplifier input terminals.

6. The programmable analog integrated circuit of claim 1 further comprising:

a differential output digital to analog converter, the differential output digital to analog converter having a plurality of digital input terminals and digital to analog converter positive and negative output terminals.

7. The programmable analog integrated circuit of claim 6 wherein the analog routing pool controls the routing of signals provided by the differential output digital to analog converter.

8. The programmable analog integrated circuit of claim 6 wherein the digital to analog converter positive and negative output terminals are selectively coupled, respectively, to at least one of the first comparator positive and negative input terminals, and the second comparator positive and negative input terminals.

9. The programmable analog integrated circuit of claim 6 further comprising:

at least one of a serial peripheral interface (SPI), a Joint Test Access Group (JTAG) interface, and a parallel interface, the plurality of digital input terminals of the differential output digital to analog converter being accessible through the at least one of a serial peripheral interface (SPI), a Joint Test Access Group (JTAG) interface, and a parallel interface.

10. The programmable analog integrated circuit of claim 6 wherein the a differential output digital to analog converter further comprises:

a reference amplifier operable to provide a reference voltage at a reference amplifier output terminal;

a first multiple segment resistor string coupled to the reference amplifier output terminal, the first multiple segment resistor string including;

a first plurality of segment switches and first decode logic; and

a second multiple segment resistor string coupled in series with the first multiple segment resistor string, the second multiple segment resistor string including;

a second plurality of segment switches and second decode logic.

11. The programmable analog integrated circuit of claim 1 wherein the double differential comparator further comprises:

a differential input comparator having first and second floating gate input terminals; and

a capacitively coupled input stage coupled to the differential input comparator, the capacitively coupled input stage including a plurality of input terminals and providing to the first and second floating gate input terminals a weighted sum of signals applied to the plurality of input terminals.

12. The programmable analog integrated circuit of claim 11 wherein the a differential input comparator further comprises a first p-channel MOSFET and a second p-channel MOSFET, the first and second p-channel MOSFETs being coupled together at their respective source terminals, wherein the first floating gate input terminal is coupled to the gate of the first p-channel MOSFET, and wherein the second floating gate input terminal is coupled to the gate of the second p-channel MOSFET.

13. The programmable analog integrated circuit of claim 11 wherein the capacitively coupled input stage further comprises:

a first comparator positive input capacitor coupled between the first comparator positive input terminal and the first floating gate input terminal;

a first comparator negative input capacitor coupled between the first comparator negative input terminal and the second floating gate input terminal;

a second comparator positive input capacitor coupled between the second comparator positive input terminal and the second floating gate input terminal; and

a second comparator negative input capacitor coupled between the second comparator negative input terminal and the first floating gate input terminal.

14. The programmable analog integrated circuit of claim 13 wherein at least one of the input capacitors has at least one trim capacitor coupled in parallel with the at least one of the input capacitors.

15. The programmable analog integrated circuit of claim 14 wherein the at least one trim capacitor includes a plurality of trim capacitors, each of the plurality of trim capacitors coupled in series with an associated manufacturer-controlled switch, and each of the plurality of trim capacitors and associated manufacturer-controlled switches being coupled in parallel with each other of the plurality of trim capacitors coupled in series with an associated manufacturer-controlled switch.

16. The programmable analog integrated circuit of claim 15 wherein the plurality of trim capacitors are numerically weighted.

17. The programmable analog integrated circuit of claim 13 further comprising:

a first hysteresis capacitor selectively coupled in parallel with the second comparator positive input capacitor; and

a second hysteresis capacitor selectively coupled in parallel with the second comparator negative input capacitor.

18. The programmable analog integrated circuit of claim 1 further comprising:

a second double differential comparator, the double differential comparator including;

first second comparator positive and negative input terminals;

second second comparator positive and negative input terminals; and

second comparator positive and negative output terminals, the second double differential comparator providing a logic high output signal at the second comparator output terminals when a third differential voltage applied to the first second comparator input terminals is positive with respect to a fourth differential voltage applied to the second second comparator input terminals;

wherein the analog routing pool controls the routing of signals provided by and to the second double differential comparator.

19. A double differential comparator comprising:

first and second MOSFETs coupled at their sources to form a differential pair;

first comparator positive and negative input terminals, the first comparator positive input terminal coupled to the gate of the first MOSFET and the first comparator negative input terminal coupled to the gate of the second MOSFET;

second comparator positive and negative input terminals, the second comparator positive input terminal coupled to the gate of the second MOSFET and the second comparator negative input terminal coupled to the gate of the first MOSFET; and

comparator positive and negative output terminals,

the double differential comparator providing a logic high output signal at the comparator output terminals when a first differential voltage applied to the first comparator input terminals is positive with respect to a second differential voltage applied to the second comparator input terminals.

20. A double differential comparator comprising:

a differential input comparator having first and second floating gate input terminals;

a capacitively coupled input stage coupled to the differential input comparator, the capacitively coupled input stage including first comparator positive and negative input terminals and second comparator positive and negative input terminals providing to the first and second floating gate input terminals a weighted sum of signals applied to the comparator input terminals; and

comparator positive and negative output terminals,

the double differential comparator providing a logic high output signal at the comparator output terminals when a first differential voltage applied to the first comparator input terminals is positive with respect to a second differential voltage applied to the second comparator input terminals.

21. The double differential comparator of claim 20 wherein the differential input comparator further comprises a first p-channel MOSFET and a second p-channel MOSFET, the first and second p-channel MOSFETs being coupled together at their respective source terminals, wherein the first floating gate input terminal is coupled to the gate of the first p-channel MOSFET, and wherein the second floating gate input terminal is coupled to the gate of the second p-channel MOSFET.

22. The double differential comparator of claim 20 wherein the capacitively coupled input stage further comprises:

a first comparator positive input capacitor coupled between the first comparator positive input terminal and the first floating gate input terminal;

a first comparator negative input capacitor coupled between the first comparator negative input terminal and the second floating gate input terminal;

a second comparator positive input capacitor coupled between the second comparator positive input terminal and the second floating gate input terminal; and

a second comparator negative input capacitor coupled between the second comparator negative input terminal and the first floating gate input terminal.

23. The double differential comparator of claim 22 wherein at least one of the input capacitors has at least one trim capacitor coupled in parallel with the at least one of the input capacitors.

24. The double differential comparator of claim 23 wherein the at least one trim capacitor includes a plurality of trim capacitors, each of the plurality of trim capacitors coupled in series with an associated manufacturer-controlled switch, and each of the plurality of trim capacitors and associated manufacturer-controlled switches being coupled in parallel with each other of the plurality of trim capacitors coupled in series with an associated manufacturer-controlled switch.

25. The double differential comparator of claim 24 wherein the plurality of trim capacitors are numerically weighted.

26. The double differential comparator of claim 22 further comprising:

a first hysteresis capacitor selectively coupled in parallel with the second comparator positive input capacitor; and

a second hysteresis capacitor selectively coupled in parallel with the second comparator negative input capacitor.