Method for testing a USB port and the device for the same
First Claim
Patent Images
1. A method for testing a USB port, which comprises the steps of:
- reading in an I/O base address of a USB host controller;
initializing a parallel port;
testing whether the GND signal is disconnected by setting the D1 and D2 pins of the parallel at high voltages and measuring the D3 pin of the parallel port;
testing whether the VCC signal is disconnected by setting the D1 and D2 pins of the parallel at low voltages and measuring the D0 pin of the parallel port;
testing whether the D+ and D−
form a short circuit with GND by setting the D1 and D2 pins of the parallel port at high voltages and reading the statuses of the D+ and D−
from the USB host controller;
testing whether D+ and D−
form a short circuit with VCC by setting the D1 and D2 pins of the parallel port at low voltages and reading the statuses of the D+ and D−
from the USB host controller;
testing whether D+ and D−
are disconnected by setting the D1 and D2 pins of the parallel port at low voltages and then at high voltages and reading the statuses of the D+ and D−
from the USB host controller;
testing whether D+ and D−
form a short circuit by setting the D1 and D2 pins of the parallel port first at high voltages and then at low voltages and reading the statuses of the D+ and D−
from the USB host controller; and
displaying the test result.
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Abstract
A method for testing a USB port and the device for the same. The VCC and GND power lines of the USB port and the twisted paired signal lines of D+ and D− are connected with the corresponding terminals on a parallel port so as to test the connection between the USB port and the USB host controller. The invention also discloses the corresponding device.
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Citations
12 Claims
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1. A method for testing a USB port, which comprises the steps of:
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reading in an I/O base address of a USB host controller;
initializing a parallel port;
testing whether the GND signal is disconnected by setting the D1 and D2 pins of the parallel at high voltages and measuring the D3 pin of the parallel port;
testing whether the VCC signal is disconnected by setting the D1 and D2 pins of the parallel at low voltages and measuring the D0 pin of the parallel port;
testing whether the D+ and D−
form a short circuit with GND by setting the D1 and D2 pins of the parallel port at high voltages and reading the statuses of the D+ and D−
from the USB host controller;
testing whether D+ and D−
form a short circuit with VCC by setting the D1 and D2 pins of the parallel port at low voltages and reading the statuses of the D+ and D−
from the USB host controller;
testing whether D+ and D−
are disconnected by setting the D1 and D2 pins of the parallel port at low voltages and then at high voltages and reading the statuses of the D+ and D−
from the USB host controller;
testing whether D+ and D−
form a short circuit by setting the D1 and D2 pins of the parallel port first at high voltages and then at low voltages and reading the statuses of the D+ and D−
from the USB host controller; and
displaying the test result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification
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Current AssigneeInventec Corporation
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Original AssigneeInventec Corporation
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InventorsLu, Ming, Lin, Kuang-Shin, Chen, Tong S
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Primary Examiner(s)VO, TIM T
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Application NumberUS09/706,840Time in Patent Office1,211 DaysField of Search710/305, 710/313, 714/38, 713/1, 713/2US Class Current710/305CPC Class CodesG06F 11/221 to test buses, lines or int...G06F 13/4068 Electrical coupling
