Interlaced memory device with random or sequential access

• US 6,701,419 B2
• Filed: 10/15/2001
• Issued: 03/02/2004
• Est. Priority Date: 10/18/2000
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Tomaiuolo, Francesco, Nicosia, Salvatore, Pascucci, Luigi
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US09/977,561
• Publication Number:
  US 20020087817A1
• Time in Patent Office: 869 Days
• Field of Search: 711/5, 711/157, 365/230.03, 365/233, 365/233.5, 365/239
• US Class Current: 711/157
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

Claims

1. An interleaved memory readable in a sequential access synchronous mode and in a random access asynchronous mode, said interleaved memory comprising:

first and second banks of memory cells;

at least one input address buffer;

a first address counter connected between said first bank of memory cells and said at least one input address buffer, and a second address counter connected between said second bank of memory cells and said at least one input address buffer;

a first sensing circuit connected to said first bank of memory cells, and a second sensing circuit connected to said second bank of memory cells;

an address transition detector connected to said at least one input address buffer for producing a detection pulse based upon a change in an input address received by said at least one input address buffer;

a delay circuit connected to said address transition detector for delaying and extending duration of the detection pulse for producing a detection signal;

at least one output data buffer;

an internal data bus for transferring data in said first and second sensing circuits to said at least one output data buffer under control of a load signal specific to one of said first and second banks of memory cells; and

a control circuit having inputs for receiving external command signals for enabling the memory and for enabling said at least one output data buffer, said control circuit for

generating the load signal,

discriminating a requested reading mode based upon an internally generated synchronous read start signal and an asynchronous read start signal, with the synchronous read start signal being active when a new address coincides with an address stored in one of said first and second address counters based upon enabling of the detection signal,

the asynchronous read start signal assuming a first logic state when the new address differs from addresses stored in said first and second address counters based upon the enabling of the detection signal, with a transition to the first logic state of the asynchronous read start signal enabling acquisition of an address in said first and second address counters and start of a new random access asynchronous read cycle with a simultaneous activation of said first and second sensing circuits, with the external command signal for enabling said at least one output data buffer acting as an enabling signal for transferring data read from said first and second banks of memory cells currently in priority to said at least one output data buffer, based upon a value of a least significant address bit of the input address, and

returning of the asynchronous read start signal to a second logic state causes after a certain delay switching to the sequential access synchronous read mode by generating, within said control circuit, a first increment pulse for said first or second address counter of said first or second bank of memory cells currently not in priority, for implementing an outphasing between said first and second bank of memory cells from a first synchronous mode read cycle depending on the value assumed by the least significant address bit, and progressing under control of the synchronous read start signal and under control of a third command signal for loading data in said at least one output data buffer for a sequential reading of stored data, with the third command signal being internally generated in said control circuit.

2. An interleaved memory according to claim 1, wherein said first and second sensing circuits are functionally independent from each other.

3. An interleaved memory according to claim 1, further comprising:

a first data register connected between said first sensing circuit and said at least one output data buffer; and

a second data register connected between said second sensing circuit and said at least one output data buffer.

4. An interleaved memory according to claim 1, wherein the asynchronous read start signal assumes the first logic state when a restart signal for an asynchronous reading produced by said control circuit is active.

5. An interleaved memory according to claim 4, wherein said control circuit comprises:

an increment circuit for generating increment pulses for said first and second address counters, and being stimulated by the asynchronous read start signal during a first asynchronous reading and by the load pulse during synchronous readings successive to the first asynchronous read;

a load circuit for producing load commands equal to the load pulse based upon the least significant address bit identifying one of said first and second banks of memory cells, with the load pulse being produced based upon the asynchronous read start signal and transfer signals of data read from said first and second banks of memory cells; and

a restart circuit for producing the restart signal for the asynchronous reading when a change of address occurs before an end of a synchronous or asynchronous read cycle.

6. An interleaved memory according to claim 5, wherein said increment circuit comprises:

a latch being set by the asynchronous read start signal and being reset by the load pulse, and producing a discrimination signal for discriminating an asynchronous read from a successive synchronous read;

a first multiplexer controlled by the discrimination signal and having an input for receiving a delayed replica of the asynchronous read start signal and an inverted load pulse;

a pulse generator connected in cascade to said first multiplexer for producing a pulse having a pre-established duration when an output of said first multiplexer is enabled;

a logic circuit for producing a general increment pulse as a logic AND between the pulse produced by said pulse generator and an inverted asynchronous read start signal delayed on a transition edge from a first logic state to a second logic state, and a logic OR between the least significant address bit identifying one of the said first and second banks of memory cells and an inverted discriminating signal;

a second multiplexer controlled by the discrimination signal and having an input for receiving the least significant address bit and an inverted least significant address bit; and

a logic circuit for producing the increment pulse as a logic AND between the general increment pulse and an inverted output signal from said second multiplexer, or as a logic AND between the general increment pulse and the output signal from said second multiplexer.

7. An interleaved memory according to claim 6, wherein said restart circuit comprises:

a pulse generator for producing a control pulse based upon activation of the external command signal for enabling the memory;

a first latch being set by an inverted second detection signal obtained as a logic AND between a control pulse and the detection pulse, and being reset by a reset signal obtained as logic AND between the general increment pulse and an inverted discrimination signal;

a second latch being set by a logic AND of an output of said first latch and a second detection signal, and being reset by a logic NOR of an output of said first latch and the reset signal; and

a logic circuit for producing the restart signal of an asynchronous read as a logic OR between an inverted control pulse and a logic AND between the output of said second latch and the inverted second detection signal.

8. An interleaved memory according to claim 7, wherein said load circuit comprises:

a first multiplexer controlled by the least significant address bit being input with a pair of transfer signals of data read from said first and second banks of memory cells;

a first latch being set by the synchronous read start signal, and reset by the load pulse for producing a synchronization signal;

a second multiplexer controlled by the discrimination signal and having an input for receiving a pair of logic signals formed by a logic AND between an inverted command signal for enabling said at least one output data buffer and an inverted output of said first multiplexer, and by a logic AND between the inverted command signal for enabling said at least one output data buffer and an inverted output of said first multiplexer and the synchronization signal;

a pulse generator in cascade to said second multiplexer for producing a pulse having a pre-established duration upon activation of said second multiplexer;

a first logic circuit producing the load pulse as a logic AND between the pulse produced by said pulse generator and an inverted asynchronous read start signal delayed on a transition edge from the first logic state to the second logic state; and

a second logic circuit for respectively producing the load commands as a logic AND between the least significant address bit and the load pulse, and as a logic AND between the inverted least significant address bit and the load pulse.

9. An interleaved memory according to claim 8, wherein said at least one output data buffer comprises a precharge circuit for precharging an output node to an intermediate voltage between voltages corresponding to two different logic states of the data being output.

10. An interleaved memory readable in a sequential access synchronous mode and in a random access asynchronous mode, the interleaved memory comprising:

first and second banks of memory cells;

at least one input address buffer;

a first address counter connected between said first bank of memory cells and said at least one input address buffer, and a second address counter connected between said second bank of memory cells and said at least one input address buffer;

a first sensing circuit connected to said first bank of memory cells, and a second sensing circuit connected to said second bank of memory cells;

an address transition detector circuit connected to said at least one input address buffer for detecting a change in an input address received thereby, said address transition detector circuit operating as a synchronous clock for the interleaved memory;

at least one output data buffer; and

a control circuit having inputs for receiving external command signals for enabling the memory and for enabling said at least one output data buffer, said control circuit for recognizing the sequential access synchronous mode or the random access asynchronous mode by enabling a comparison of a currently received input address with an address stored in said first and second address counters.

11. An interleaved memory according to claim 10, wherein said at least one output data buffer comprising a precharge circuit for precharging an output node to an intermediate voltage between voltages corresponding to two different logic states of data being output.

12. An interleaved memory according to claim 10, wherein said address transition detector circuit comprises:

an address transition detector connected to said at least one input address buffer for producing a detection pulse based upon the change in the received input address; and

a delay circuit connected to said address transition detector for delaying and extending duration of the detection pulse for producing a detection signal.

13. An interleaved memory according to claim 12, further comprising an internal data bus for transferring data in said first and second sensing circuits to said at least one output data buffer under control of a load signal specific to one of said first and second banks of memory cells.

14. An interleaved memory according to claim 13, wherein the control circuit generates the load signal, and discriminates a requested reading mode based upon an internally generated synchronous read start signal and an asynchronous read start signal, with the synchronous read start signal being active when a new address coincides with an address stored in one of said first and second address counters based upon enabling of the detection signal.

15. An interleaved memory according to claim 14, wherein the asynchronous read start signal assumes a first logic state when the new address differs from addresses stored in said first and second address counters based upon the enabling of the detection signal, with a transition to the first logic state of the asynchronous read start signal enabling acquisition of an address in said first and second address counters, and start of a new random access asynchronous read cycle with a simultaneous activation of said first and second sensing circuits, with the external command signal for enabling said at least one output data buffer acting as an enabling signal for transferring data read from said first and second banks of memory cells currently in priority to said at least one output data buffer, based upon a value of a least significant address bit of the input address.

16. An interleaved memory according to claim 15, wherein the return of the asynchronous read start signal to a second logic state causes after a certain delay switching to the sequential access synchronous read mode by generating, within said control circuit, a first increment pulse for said first or second address counter of said first or second bank of memory cells currently not in priority, for implementing an outphasing between said first and second bank of memory cells from a first synchronous mode read cycle depending on the value assumed by the least significant address bit, and progressing under control of the synchronous read start signal and under control of a third command signal for loading data in said at least one output data buffer, with the third command signal being internally generated in said control circuit.

17. An interleaved memory according to claim 10, wherein said first and second sensing circuits are functionally independent from each other.

18. An interleaved memory according to claim 10, further comprising:

a first data register connected between said first sensing circuit and said at least one output data buffer; and

a second data register connected between said second sensing circuit and said at least one output data buffer.

19. An interleaved memory according to claim 10, wherein the asynchronous read start signal assumes the first logic state even when a restart signal for an asynchronous reading produced by the control circuit is active.

20. An interleaved memory according to claim 10, wherein said control circuit comprises:

an increment circuit for generating increment pulses for said first and second address counters, and being stimulated by the asynchronous read start signal during a first asynchronous reading and by the load pulse during synchronous readings successive to the first asynchronous read;

a load circuit for producing load commands equal to the load pulse based upon the least significant address bit identifying one of said first and second banks of memory cells, with the load pulse being produced based upon the asynchronous read start signal and transfer signals of data read from said first and second banks of memory cells; and

a restart circuit for producing the restart signal for the asynchronous reading when a change of address occurs before an end of a synchronous or asynchronous read cycle.

21. An interleaved memory according to claim 20, wherein the increment circuit comprises:

a latch being set by the asynchronous read start signal and being reset by the load pulse, and producing a discrimination signal for discriminating an asynchronous read from a successive synchronous read;

a first multiplexer controlled by the discrimination signal and having an input for receiving a delayed replica of the asynchronous read start signal and an inverted load pulse;

a pulse generator connected in cascade to said first multiplexer for producing a pulse having a pre-established duration when an output of said first multiplexer is enabled;

a logic circuit for producing a general increment pulse as a logic AND between the pulse produced by said pulse generator and an inverted asynchronous read start signal delayed on a transition edge from a first logic state to a second logic state, and a logic OR between the least significant address bit identifying one of said first and second banks of memory cells and an inverted discrimination signal;

a second multiplexer controlled by the discrimination signal and having an input for receiving the least significant address bit and an inverted least significant address bit; and

a logic circuit for producing the increment pulse as a logic AND between the general increment pulse and an inverted output signal from said second multiplexer, or as a logic AND between the general increment pulse and the output signal from said second multiplexer.

22. An interleaved memory according to claim 21, wherein said restart circuit comprises:

a pulse generator for producing a control pulse based upon activation of the external command signal for enabling the memory;

a first latch being set by an inverted second detection signal obtained as a logic AND between a control pulse and the detection pulse, and being reset by a reset signal obtained as logic AND between the general increment pulse and an inverted discrimination signal;

a second latch being set by a logic AND of an output of said first latch and of a second detection signal, and being reset by a logic NOR of an output of said first latch and the reset signal; and

a logic circuit for producing the restart signal of an asynchronous read as a logic OR between an inverted control pulse and a logic AND between the output of said second latch and the inverted second detection signal.

23. An interleaved memory according to claim 22, wherein said load circuit comprises:

a first multiplexer controlled by the least significant address bit being input with a pair of transfer signals of data read from said first and second banks of memory cells;

a first latch being set by the synchronous read start signal, and reset by the load pulse for producing a synchronization signal;

a second multiplexer controlled by the discrimination signal and having an input for receiving a pair of logic signals formed by a logic AND between an inverted command signal for enabling said at least one output data buffer and an inverted output of said first multiplexer, and by a logic AND between the inverted command signal for enabling said at least one output data buffer and an inverted output of said first multiplexer and the synchronization signal;

a pulse generator in cascade to said second multiplexer for producing a pulse having a pre-established duration upon activation of said second multiplexer;

a first logic circuit producing the load pulse as a logic AND between the pulse produced by said pulse generator and an inverted asynchronous read start signal delayed on a transition edge from the first logic state to the second logic state; and

a second logic circuit for respectively producing the load commands as a logic AND between the least significant address bit and the load pulse, and as a logic AND between the inverted least significant address bit and the load pulse.

24. A method for operating an interleaved memory readable in a sequential access synchronous mode and in a random access asynchronous mode, the interleaved memory comprising first and second banks of memory cells, at least one input address buffer, a first address counter connected between the first bank of memory cells and the at least one input address buffer, a second address counter connected between the second bank of memory cells and the at least one input address buffer, a first sensing circuit connected to the first bank of memory cells, a second sensing circuit connected to the second bank of memory cells, and at least one output data buffer, the method comprising:

detecting a change in an input address received by the at least one input address buffer using an address transition detector circuit connected thereto, with the address transition detector circuit operating as a synchronous clock for the interleaved memory; and

recognizing the sequential access synchronous mode or the random access asynchronous mode by comparing a currently received input address with an address stored in the first and second address counters.

25. A method according to claim 24, further comprising precharging an output node to an intermediate voltage between voltages corresponding to two different logic states of data being output.

26. A method according to claim 24, wherein the detecting comprises:

producing a detection pulse based upon the change in the input address received by the at least one input address buffer; and

delaying and extending duration of the detection pulse for producing a detection signal.

27. A method according to claim 26, further comprising transferring data in the first and second sensing circuits to the at least one output data buffer under control of a load signal specific to one of the first and second banks of memory cells.

28. A method according to claim 27, wherein the recognizing is performed using a control circuit for generating the load signal;

and

discriminating a requested reading mode based upon an internally generated synchronous read start signal and an asynchronous read start signal, with the synchronous read start signal being active when a new address coincides with an address stored in one of the first and second address counters based upon enabling of the detection signal.

29. A method according to claim 28, wherein the asynchronous read start signal assumes a first logic state when the new address differs from addresses stored in the first and second address counters based upon the enabling of the detection signal, with a transition to the first logic state of the asynchronous read start signal enabling acquisition of an address in the first and second address counters, and start of a new random access asynchronous read cycle with a simultaneous activation of the first and second sensing circuits, with an external command signal for enabling the at least one output data buffer acting as an enabling signal for transferring data read from the first and second banks of memory cells currently in priority to the at least one output data buffer, based upon a value of a least significant address bit of the input address.

30. A method according to claim 29, wherein the return of the asynchronous read start signal to a second logic state causes after a certain delay switching to the sequential access synchronous read mode by generating, within the control circuit, a first increment pulse for the first or second address counter of the first or second bank of memory cells currently not in priority, implementing an outphasing between the first and second bank of memory cells from a first synchronous mode read cycle depending on the value assumed by the least significant address bit, progressing under control of the synchronous read start signal and under control of a third command signal for loading data in the at least one output data buffer, with the third command signal being internally generated in the control circuit.

31. A method according to claim 24, wherein the first and second sensing circuits are functionally independent from each other.

32. A method according to claim 24, wherein the asynchronous read start signal assumes a first logic state when a restart signal for an asynchronous reading produced by the control circuit is active.