User defined names for registers in memory banks derived from configurations

• US 6,701,487 B1
• Filed: 11/19/2001
• Issued: 03/02/2004
• Est. Priority Date: 11/19/2001
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG), Itochu Corporation, The Sailor Pen Co., Ltd.
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ogami, Kenneth Y., Roe, Steve
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US09/989,775
• Time in Patent Office: 834 Days
• Field of Search: 716/1-14, 395/500, 395/180
• US Class Current: 716/117
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A system and method for displaying a customized register name, an associated physical address, and an associated value in a software design tool. The customized register name identifies a user module and a configuration register of the user module. The user module is a circuit design to be realized in a programmable electronic circuit. The customized register name can be automatically generated based on the user module name and the configuration register name. The customized register name can also be modified as a unique identifier by a user. The physical address and value of the configuration register can be automatically updated based on modifications of the user module and/or hardware resources assigned to the user module.

Claims

1. A method of designing an integrated circuit comprising:

a. generating a customized register name associated with a user module and a register;

b. linking a physical address of the register to the customized register name; and

c. linking a value associated with the register to the customized register name.

2. The method according to claim 1 further comprising updating the physical address of the register.

3. The method according to claim 1 further comprising updating the value associated with the register.

4. The method according to claim 1 wherein generating the customized register name further comprises combining a name of the user module and a name of a function of the register as the customized register name.

5. The method according to claim 1 wherein generating the customized register name further comprises creating a unique identifier.

6. The method according to claim 1 further comprising displaying a table of a plurality of customized register names, a plurality of corresponding physical addresses, and a plurality of corresponding values.

7. The method according to claim 6 wherein displaying further comprises organizing the table according to the plurality of corresponding physical addresses.

8. The method according to claim 6 wherein displaying further comprises organizing the table according to the plurality of corresponding values.

9. A system for designing an integrated circuit comprising:

a. a resource utilization detector configured to find a user module;

b. a resource placement locator coupled to the resource utilization detector configured to locate a hardware resource for utilization by the user module; and

c. a register window coordinator coupled to the resource placement locator configured to generate a customized register name associated with the user module and a configuration register.

10. The system according to claim 9 further comprising a display coupled to the register window coordinator for viewing the customized register name.

11. The system according to claim 9 wherein the register window coordinator is also configured to associate a physical address of the configuration register with the customized register name.

12. The system according to claim 11 wherein the register window coordinator is also configured to update the physical address periodically.

13. The system according to claim 9 wherein the register window coordinator is also configured to associate a value of the configuration register with the customized register name.

14. The system according to claim 13 wherein the register window coordinator is also configured to update the value periodically.

15. A system for designing an integrated circuit comprising:

a. a resource utilization detector configured to find a user module; and

b. a register window coordinator coupled to the resource utilization detector configured to generate a customized register name associated with the user module and a configuration register, to associate a value of the configuration register with the customized register name, and to associate a physical address of the configuration register with the customized register name.

16. The system according to claim 15 further comprising a display coupled to the register window coordinator configured to show the customized register name, the physical address, and the value.

17. A method of generating program code for a programmable electronic device comprising:

a) associating a register textual label with a configuration register of an electronic circuit design;

b) associating said electronic circuit design with a first programmable hardware resource, said first programmable hardware resource comprising first physical register addresses;

c) automatically associating said configuration register with a physical address of said first physical register addresses; and

d) rendering a display comprising said textual label of said configuration register and said physical address of said first physical register addresses.

18. A method as described in claim 17 further comprising:

e) associating said electronic circuit design with a second programmable hardware resource, said second programmable hardware resource comprising second physical register addresses;

f) automatically associating said configuration register with a new physical address of said second physical register addresses; and

g) updating said display to comprise said textual label of said configuration register and said new physical address of said second physical register addresses.

19. A method as described in claim 18 wherein said display is a textual grid display further comprising a plurality of textual labels and associated respective physical addresses.

20. A method as described in claim 17 further comprising automatically generating source code for programming said programmable electronic device to implement said electronic circuit design, said source code comprising mapping between said textual label and said physical address.

21. A computer system comprising:

a processor coupled to a bus and a memory coupled to said bus and comprising instructions for implementing a method of generating program code for a programmable electronic device comprising;

a) associating a register textual label with a configuration register of an electronic circuit design;

b) associating said electronic circuit design with a first programmable hardware resource, said first programmable hardware resource comprising first physical register addresses;

c) automatically associating said configuration register with a physical address of said first physical register addresses; and

d) rendering a display comprising said textual label of said configuration register and said physical address of said first physical register addresses.

22. A computer system as described in claim 21 further comprising:

e) associating said electronic circuit design with a second programmable hardware resource, said second programmable hardware resource comprising second physical register addresses;

f) automatically associating said configuration register with a new physical address of said second physical register addresses; and

g) updating said display to comprise said textual label of said configuration register and said new physical address of said second physical register addresses.

23. A computer system as described in claim 22 wherein said display is a textual grid display further comprising a plurality of textual labels and associated respective physical addresses.

24. A computer system as described in claim 21 further comprising automatically generating source code for programming said programmable electronic device to implement said electronic circuit design, said source code comprising mapping between said textual label and said physical address.