Method for effective capacitance calculation of interconnect portion and delay calculation of electronic circuit
First Claim
1. A calculation method of effective capacitance equivalent to delay with load in interconnections between electronic circuit elements comprising the steps of:
- substituting the impedance of an interconnection placed between a first node of an output section of a first electronic circuit element and a second node of an input section of a second electronic circuit element with an equivalent circuit of RCπ
type having an equivalent capacitance C1 placed on the side of said second node and an equivalent capacitance C2 placed on the side of said first node and an equivalent resistance R placed between said first node and said second node; and
when defining delay from said first electronic circuit element to said first node as t0, calculating the effective capacitance Ceff viewed from said first node in accordance with an equation Ceff=C2+C1·
t0/(t0+R·
C1).
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Abstract
The present invention provides a high-speed processing and high precision delay calculation method of semiconductor integrated circuit devices having a plurality of cells and interconnections connecting therebetween, with less data to be obtained prior to delay calculation. The method comprises the steps of: calculating temporary delay T0 that is the delay of the cell on the basis of total load capacitance Ct of the capacitance values connected to the output of the cell; calculating the voltage Vc at the node connected to the load capacitance C connected to the output of the cell at the temporary delay T0; calculating effective load capacitance Ceff by multiplying the ratio of the voltage Vc to the voltage Vtb defining the delay with the capacitance C; calculating the cell delay Tc on the basis of the effective load capacitance Ceff.
17 Citations
6 Claims
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1. A calculation method of effective capacitance equivalent to delay with load in interconnections between electronic circuit elements comprising the steps of:
-
substituting the impedance of an interconnection placed between a first node of an output section of a first electronic circuit element and a second node of an input section of a second electronic circuit element with an equivalent circuit of RCπ
type having an equivalent capacitance C1 placed on the side of said second node and an equivalent capacitance C2 placed on the side of said first node and an equivalent resistance R placed between said first node and said second node; and
when defining delay from said first electronic circuit element to said first node as t0, calculating the effective capacitance Ceff viewed from said first node in accordance with an equation Ceff=C2+C1·
t0/(t0+R·
C1).- View Dependent Claims (2, 3)
the delay t0 from said first electronic circuit element to said first node is defined by multiplying the sum of said equivalent capacitance C1 and said equivalent capacitance C2 (C1+C2) with a delay variation coefficient Ron predetermined with respect to the load capacitance of said first electronic circuit element.
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3. A method of delay calculation in an electronic circuit, comprising the step of:
calculating delay T of said electronic circuit on the basis of the effective capacitance Ceff calculated in accordance with claim 1, using input transition time TI of said first electronic circuit element and delay parameters a1, b1, c1 and d1 in accordance with an equation T=a1·
TI·
Ceff+b1·
Ceff+c1·
TI+d1.
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4. A method of calculating an effective capacitance equivalent to delay with load in an interconnection between integrated circuit (IC) elements in an integrated circuit (IC) device by substituting the impedance of the interconnection placed between first and second nodes with a RC type equivalent circuit having a capacitor C1, a resistor R and a capacitor C2, wherein the delay is defined from a first IC element to said first node as “
- t0”
, and wherein the effective capacitance is calculated as viewed from said first node using C2+C1·
“
t0”
/(“
t0”
+R·
C1). - View Dependent Claims (5, 6)
- t0”
Specification
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- Resources
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi, Ltd.
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InventorsOhkubo, Norio
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Primary Examiner(s)Whitmore, Stacy
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Application NumberUS09/678,660Time in Patent Office1,245 DaysField of Search716/1, 716/2, 716/6, 703/2, 703/4, 703/19US Class Current716/113CPC Class CodesG06F 30/33 Design verification, e.g. f...
