High-pressure anneal process for integrated circuits

• US 6,703,327 B2
• Filed: 06/13/2002
• Issued: 03/09/2004
• Est. Priority Date: 01/22/1996
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lane, Richard H., Wald, Phillip G.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): KILDAY, LISA A
• Application Number:
  US10/128,757
• Publication Number:
  US 20020151128A1
• Time in Patent Office: 635 Days
• Field of Search: 438/660, 438/775, 438/791, 438/795, 438/904, 257/297
• US Class Current: 438/584
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: Y10S 438/904 Charge carrier lifetime control
• CPC Class Codes: Y10S 438/908 Utilizing cluster apparatus

Abstract

An improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Claims

1. A processing method for a semiconductor workpiece having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof, comprising:

providing a semiconductor workpiece having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof, said silicon nitride film deposited as a final layer over at least a portion of said semiconductor workpiece; and

annealing said semiconductor workpiece in a forming gas at a pressure greater than an ambient pressure, said workpiece having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof, wherein said step of annealing said semiconductor workpiece comprises annealing said semiconductor workpiece in said forming gas at a pressure substantially ranging from about 10 to about 25 atmospheres.

2. The method in claim 1, wherein said step of annealing said semiconductor workpiece comprises annealing said semiconductor workpiece in said forming gas at a pressure greater than one atmosphere.

3. A processing method for an integrated circuit having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate, comprising:

providing an integrated circuit having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate, said silicon nitride film deposited as a final layer over at least a portion of said integrated circuit;

placing said integrated circuit having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate in a chamber containing hydrogen; and

generating a first pressure inside said chamber, said first pressure being greater than a second pressure outside of said chamber, wherein said step of annealing said semiconductor workpiece comprises annealing said semiconductor workpiece in said forming gas at a pressure substantially ranging from about 10 to about 25 atmospheres.

4. The method of claim 3, wherein said step of generating a first pressure comprises generating a first pressure greater than a general atmospheric pressure.

5. A process treatment method for a semiconductor wafer comprising:

providing said semiconductor wafer having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate thereon and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor wafer;

performing a first anneal in a first reducing atmosphere at room pressure for a first length of time at a first temperature on said semiconductor wafer having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate thereon and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor wafer; and

exposing said semiconductor wafer having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate thereon and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor wafer to a second anneal in a second reducing atmosphere at a second pressure that is greater than said room pressure, wherein said step of annealing said semiconductor workpiece comprises annealing said semiconductor workpiece in said forming gas at a pressure substantially ranging from about 10 to about 25 atmospheres.

6. The method in claim 5, further comprising a step of foregoing said first anneal.

7. The method in claim 6, wherein said step of exposing said semiconductor wafer to a second anneal comprises exposing said semiconductor wafer to said second anneal in a second reducing atmosphere that is similar in composition to said first reducing atmosphere.

8. The method in claim 7, wherein said step of exposing said semiconductor wafer to a second anneal comprises exposing said semiconductor wafer to said second anneal for a second length of time that is less than said first length of time.

9. The method in claim 7, wherein said step of exposing said semiconductor wafer to a second anneal comprises exposing said semiconductor wafer to said second anneal at a second temperature that is less than said first temperature.

10. A process treatment method for a semiconductor wafer comprising:

providing a semiconductor wafer having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate thereon and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor wafer;

performing a first anneal in a first reducing atmosphere at room pressure for a first length of time at a first temperature on said semiconductor wafer having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate thereon and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor wafer; and

exposing said semiconductor wafer having at least one transistor gate structure having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate thereon and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor wafer to a second anneal in a second reducing atmosphere at a second pressure that is greater than said room pressure, wherein said step of annealing said semiconductor workpiece comprises annealing said semiconductor workpiece in said forming gas at a pressure substantially ranging from about 10 to about 25 atmospheres.

11. The method in claim 10, further comprising a step of foregoing said first anneal.

12. The method in claim 11, wherein said step of exposing said semiconductor wafer to a second anneal comprises exposing said semiconductor wafer to said second anneal in a second reducing atmosphere that is similar in composition to said first reducing atmosphere.

13. The method in claim 12, wherein said step of exposing said semiconductor wafer to a second anneal comprises exposing said semiconductor wafer to said second anneal for a second length of time that is less than said first length of time.

14. The method in claim 13, wherein said step of exposing said semiconductor wafer to a second anneal comprises exposing said semiconductor wafer to said second anneal at a second temperature that is less than said first temperature.