Memory structure and method making
First Claim
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1. A memory structure comprising a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections, each said intersection including an electrically linear resistive element in series with a voltage breakdown element, wherein the voltage breakdown element includes an unpatterned antifuse.
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Abstract
A memory structure has a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections. Each intersection includes an electrically linear resistive element in series with a voltage breakdown element.
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Citations
30 Claims
- 1. A memory structure comprising a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections, each said intersection including an electrically linear resistive element in series with a voltage breakdown element, wherein the voltage breakdown element includes an unpatterned antifuse.
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9. A memory structure comprising a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections, each said intersection including an electrically linear resistive element in series with a voltage breakdown element, wherein:
- each of the row and column conductors are patterned; and
the electrically linear resistive element is patterned; and
the voltage breakdown element is not patterned.
- each of the row and column conductors are patterned; and
- 10. A memory structure comprising a primary plurality of memory elements each including a row conductor connected to a column conductor by an electrically linear resistive element in series with a voltage breakdown element that is not patterned.
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20. A memory structure comprising a plurality of adjacent pairs of row conductors each having there between:
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an electrically linear resistive material;
a voltage breakdown material; and
a column conductor;
wherein the voltage breakdown material is a layer of unpatterned material between each said pair of adjacent row conductors. - View Dependent Claims (21, 22)
the electrically linear resistive material is selected from the group consisting of lightly doped microcrystalline silicon, lightly doped amorphous silicon, intrinsic silicon, refractory metal silicide nitride; and
the voltage breakdown material comprises an antifuse having a dielectric with a thickness not greater than 200 Angstroms.
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23. A memory structure comprising a plurality of adjacent pairs of patterned row conductors each having there between a voltage breakdown element sandwiched between a column conductor and an electrically linear resistive element in series with the voltage breakdown wherein:
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a layer of unpatterned material is between each said pair of adjacent row conductors; and
the layer of unpatterned material is the voltage breakdown element.- View Dependent Claims (24, 25)
the electrically linear resistive element is selected from the group consisting of lightly doped microcrystalline silicon, lightly doped amorphous silicon, intrinsic silicon, refractory metal silicide nitride; and
the voltage breakdown element comprises an antifuse having a dielectric with a thickness not greater than 200 Angstroms.
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26. A memory structure comprising a plurality of means for storing data;
- wherein;
each said means for storing data includes a row conductor connected to a column conductor by;
means for providing electrically linear resistance; and
means for programming the means for storing data;
the means for providing electrically linear resistance is in series with the means for programming the means for storing data, wherein the means for programming is not patterned. - View Dependent Claims (27, 28)
the voltage breakdown element comprises an antifuse;
each of the row and column conductors is patterned;
the electrically linear resistive element is patterned; and
the voltage breakdown element is not patterned.
- wherein;
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29. A memory storage device comprising:
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a substrate; and
a plurality of memory elements on the substrate, wherein;
each said memory element is included in a memory apparatus selected from the group consisting of a WORM memory device and a one time programmable memory device and includes;
a row conductor connected to a column conductor by an electrically linear resistive element in series with a voltage breakdown element that is not patterned. - View Dependent Claims (30)
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Specification