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Memory structure and method making

  • US 6,703,652 B2
  • Filed: 01/16/2002
  • Issued: 03/09/2004
  • Est. Priority Date: 01/16/2002
  • Status: Expired due to Fees
First Claim
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1. A memory structure comprising a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections, each said intersection including an electrically linear resistive element in series with a voltage breakdown element, wherein the voltage breakdown element includes an unpatterned antifuse.

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