CMOS device using additional implant regions to enhance ESD performance and device manufactured thereby

• US 6,703,663 B1
• Filed: 09/05/2000
• Issued: 03/09/2004
• Est. Priority Date: 02/27/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shih, Jian-Ren, Lee, Jian-Hsing, Wu, Yi-Hsun
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): BRYANT, KIESHA ROSE
• Application Number:
  US09/655,086
• Time in Patent Office: 1,281 Days
• Field of Search: 257/388, 257/314, 257/550, 257/548, 257/335, 257/264, 257/336, 257/591, 257/338
• US Class Current: 257/336
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

Claims

1. A semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprising:

the combination of a gate oxide layer and a gate electrode layer patterned into gate electrode stacks with sidewalls formed over a substrate including an NMOS FET device over a P-well in said substrate and a PMOS FET device over aN-well, P−

lightly doped source/drain regions formed in said N-well,

N−

lightly doped source/drain regions formed in said P-well,

spacers formed on said sidewalls of said gate electrode stacks,

N+ type source/drain regions in said P-well in said source/drain sites self-aligned with a said gate electrode stack,

P+ type source/drain regions in said N-well in said source/drain sites self-aligned with a said gate electrode stack,

heavily doped, counterdoped P++ regions formed directly below said P+ source/drain sites self-aligned with said gate electrode and said spacers in said N-well,

heavily doped, counterdoped N++ regions formed directly below said N+ source/drain sites self-aligned with said gate electrode and said spacers in said P-well,

deep N−

lightly doped source/drain regions formed in said N-well directly below said counterdoped P++ regions, and

deep P−

lightly doped source/drain regions formed in said P-well directly below said counterdoped N++ regions.

2. The device of claim 1 including refractory metal silicide layers formed over said gate electrode layers.

3. The device of claim 1 including:

P−

/N++ junctions are formed below said N+ source/drain regions in said P-well, and

N−

/P++ junctions are formed below said P+ source/drain regions in said N-well.

4. The device of claim 1 including:

P−

/N++ junctions are formed below said N+ source/drain regions in said P-well, and

N−

/P++ junctions are formed below said P+ source/drain regions in said N-well.

5. The device of claim 1 including:

the deep lightly doped N− and

P−

regions are formed to a depth from about 2,000 Å

to about 3,000 Å

below the surface of the substrate, and

the counterdoped N++ and counterdoped P++ regions are formed to a depth from about 1,000 Å

to about 2,000 Å

below the surface of the substrate.

6. The device of claim 1 including:

refractory metal silicide layers formed over said gate electrode layers,

refractory metal silicide layers formed over said source/drain regions,

P−

/N++ junctions are formed below said N+ source/drain regions in said P-well,

N−

/P++ junctions are formed below said P+ source/drain regions in said N-well, the deep lightly doped N− and

P−

regions are formed to a depth from about 2,000 Å

to about 3,000 Å

below the surface of the substrate, and

the counterdoped N++ and counterdoped P++ regions are formed to a depth from about 1,000 Å

to about 2,000 Å

below the surface of the substrate.

7. The device of claim 1 including:

refractory metal silicide layers formed over said source/drain regions,

P−

/N++ junctions are formed below said N+ source/drain regions in said P-well, and

N−

/P++ junctions are formed below said P+ source/drain regions in said N-well.

8. The device of claim 1 including:

refractory metal silicide layers formed over said gate electrode layers,

refractory metal silicide layers formed over said source/drain regions,

P−

/N++ junctions are formed below said N+ source/drain regions in said P-well, and

N−

/P++ junctions are formed below said P+ source/drain regions in said N-well.

9. The device of claim 8 including:

the deep lightly doped N− and

P−

regions are formed to a depth from about 2,000 Å

to about 3,000 Å

below the surface of the substrate, and

the counterdoped N++ and counterdoped P++ regions are formed to a depth from about 1,000 Å

to about 2,000 Å

below the surface of the substrate.

10. The device of claim 1 including:

the deep lightly doped N− and

P−

regions are formed to a depth from about 2,000 Å

to about 3,000 Å

below the surface of the substrate, with a concentration of phosphorus dopant in the N−

regions from about 1 E 17 atoms/cm³ to about 1 E18 atoms/cm³ and a concentration of boron dopant in the P−

regions from about 1 E 17 atoms/cm³ to about 1 E 18 atoms/cm³,

the counterdoped N++ and counterdoped P++ regions are formed to a depth from about 1,000 Å

to about 2,000 Å

below the surface of the substrate, with a concentration of phosphorus or arsenic dopant in the N++ regions from about 5 E 20 atoms/cm³ to about 1 E 21 atoms/cm³ and a concentration of boron dopant in the P++ regions from about 5 E 20 atoms/cm³ to about 1 E 21 atoms/cm³,

with the S/D regions formed with a concentration of arsenic dopant in the N+ regions from about 1 E 20 atoms/cm³ to about 5 E 20 atoms/cm³ and a concentration of boron dopant in the P+ regions from about 1 E 20 atoms/cm³ to about 5 E 20 atoms/cm³, and

with the lightly doped S/D regions formed with a concentration of phosphorus or arsenic dopant in the N−

regions from about 1 E 18 atoms/cm³ to about 1 E 20 atoms/cm³ and a concentration of boron dopant in the P−

regions from about 1 E18 atoms/cm³ to about 1 E 20 atoms/cm³.