Low-resistivity microelectromechanical structures with co-fabricated integrated circuit

• US 6,703,679 B1
• Filed: 07/07/2000
• Issued: 03/09/2004
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: Analog Devices IMI, Inc. (Analog Devices, Inc.)
• Original Assignee: Analog Devices IMI, Inc. (Analog Devices, Inc.)
• Inventors: Clark, William A., Juneau, Thor, Lemkin, Mark A., Roessig, Allen W.
• Primary Examiner(s): Eckert, George
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US09/612,482
• Time in Patent Office: 1,341 Days
• Field of Search: 257/513, 257/515, 257/507, 257/524, 735/143.2
• US Class Current: 257/513
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit

Abstract

A microfabricated device includes a substrate having a device layer and substantially filled, isolating trenches; a doped region of material formed by photolithographically defining a region for selective doping of said device layer, selectively doping said region, and thermally diffusing said dopant; circuits on said device layer formed using a substantially standard circuit technology; and at least one structure trench in the substrate which completes the definition of electrically isolated micromechanical structural elements.

Claims

1. A microelectromechanical device comprising:

a substrate having a device layer, said device layer having a first surface;

a plurality of isolation trenches having a first side and a second side formed in said device layer;

at least one active device formed in said device layer on a first side of one of said plurality of isolation trenches;

at least one structure trench formed in said substrate, said structure trench defining at least one electrically isolated movable micromechanical structure on the second side of said one of said plurality of isolation trench; and

a low-resistivity sinker of diffused dopant, said sinker extending from said first surface of said device layer towards the bottom of said at least one structure trench.

2. The device of claim 1 wherein said substrate comprises a silicon wafer and said device layer comprises silicon doped to a level of between 1 and 50 Ohm-cm.

3. The device of claim 1 wherein:

said substrate comprises a bonded-silicon wafer; and

said device layer comprises a layer of silicon doped to a level of between 1 and 50 Ohm-cm and a thickness of less than 25 microns.

4. The device of claim 1 wherein:

said substrate comprises a silicon-on-insulator wafer; and

said device layer comprises a layer of silicon doped to a level of between 1 and 50 Ohm-cm and a thickness of less than 25 microns.

5. The device of claim 1 wherein:

said substrate is selected from one of;

silicon wafer, silicon-on-insulator wafer, or bonded silicon wafer;

said device layer includes a lightly-doped layer of silicon disposed upon a heavily-doped layer of silicon; and

said dopant is of the same type as said heavily-doped layer of silicon.

6. The device of claim 1 wherein said at least one active device includes at least a MOS transistor and said sinker extends from said first surface of device layer towards the bottom of said at least one structure trench to a depth greater than the depth of a diffusion region integral to said MOS transistors.

7. The device of claim 5 wherein said sinker extends from said first surface of device layer towards the bottom of said at least one structure trench and merges with said heavily doped layer.

8. The device of claim 5 wherein the thickness of said lightly-doped layer accounts for up-diffusion in said diffusion step.

9. The device of claim 5 wherein said lightly-doped layer of silicon is formed from an epitaxially grown layer of silicon.

10. The device of claim 5 wherein:

said at least one device includes at least a MOS transistor;

said sinker extends from said first surface of device layer towards the bottom of said at least one structure trench to a depth greater than the depth of a diffusion region integral to said MOS transistors; and

at least a portion of said sinker merges with said heavily doped layer.

11. The device of claim 5 wherein said heavily-doped layer of silicon is n-type, said lightly-doped layer of silicon is n-type, and said dopant includes Phosphorous.

12. The device of claim 5 wherein said heavily-doped layer of silicon is p-type, said lightly-doped layer of silicon is p-type, and said dopant includes Boron.

13. The device of claim 5 wherein said heavily-doped layer of silicon is n-type, said lightly-doped layer of silicon is p-type, and said dopant includes Phosphorous.

14. The device of claim 5 wherein said heavily-doped layer of silicon is p-type, said lightly-doped layer of silicon is n-type, and said dopant includes Boron.

15. The device of claim 1 wherein said microelectromechanical device comprises a sensor.

16. The device of claim 1 wherein said microelectromechanical device comprises an actuator.