Graded thin films

• US 6,703,708 B2
• Filed: 12/23/2002
• Issued: 03/09/2004
• Est. Priority Date: 03/07/2000
• Status: Expired due to Term

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Werkhoven, Christiaan J., Raaijmakers, Ivo, Haukka, Suvi P.
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US10/329,658
• Publication Number:
  US 20030129826A1
• Time in Patent Office: 442 Days
• Field of Search: 257/750, 257/751, 257/762, 257/767
• US Class Current: 257/751
• CPC Class Codes: C23C 16/029 Graded interfaces
• CPC Class Codes: C23C 16/34 Nitrides C23C16/303 takes precedence
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: C23C 16/403 of aluminium, magnesium or beryllium
• CPC Class Codes: C23C 16/405 of refractory metals or yttrium
• CPC Class Codes: C23C 16/452 by activating reactive gas streams before their introduction into the reaction chamber, e.g. by ionisation or addition of reactive species
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: C23C 16/45534 Use of auxiliary reactants other than used for contributing to the composition of the main film, e.g. catalysts, activators or scavengers
• CPC Class Codes: C30B 25/14 Feed and outlet means for the gases; Modifying the flow of the reactive gases
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 : in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28562 : Selective deposition
• CPC Class Codes: H01L 21/3141 : Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3145 : formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/31612 : on a silicon body
• CPC Class Codes: H01L 21/3162 : on a silicon body
• CPC Class Codes: H01L 21/31641 : Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/3185 : of siliconnitrides
• CPC Class Codes: H01L 21/76846 : Layer combinations
• CPC Class Codes: H01L 21/76873 : for electroplating
• CPC Class Codes: H01L 21/76879 : by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2221/1089 : Stacks of seed layers
• CPC Class Codes: H01L 29/4908 : for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 428/24942 : including components having same physical characteristic in differing degree
• CPC Class Codes: Y10T 428/2495 : Thickness [relative or absolute]

Abstract

Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO₂) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a graded transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Claims

1. A barrier structure in an integrated circuit, the barrier structure comprising a graded thin film having a thickness between about 7 Å

and 200 Å

defined between an upper surface and a lower surface, the graded thin film comprising a first metal, an impurity and a second metal having a greater conductivity than the first metal, the graded thin film having a controlled composition with an increasing concentration of the second metal from the lower surface to the upper surface.

2. The barrier structure of claim 1, wherein the second metal comprises copper.

3. The barrier structure of claim 2, wherein the thin film lines a via in an insulating structure.

4. The barrier structure of claim 3, wherein the thin film further lines a dual damascene trench over the via.

5. The barrier structure of claim 4, wherein the thin film exhibits greater than about 90% step coverage of the trench and via.

6. The barrier structure of claim 5, wherein the thin film exhibits greater than about 93% step coverage of the trench and via.

7. The barrier structure of claim 6, wherein the thin film exhibits greater than about 97% step coverage of the trench and via.

8. The barrier structure of claim 1, wherein the impurity comprises nitrogen.

9. The barrier structure of claim 8, wherein the graded thin film comprises a nitride of the first metal with a decreasing metal nitride concentration from the lower surface to the upper surface.

10. The barrier structure of claim 9, wherein the nitrogen concentration is progressively varied from a highest concentration at the lower surface and a lowest concentration at the upper surface.

11. The barrier structure of claim 10, comprising a linearly graded nitrogen concentration from the lower surface to the upper surface.

12. The barrier structure of claim 1, wherein the thickness of the graded thin film is between about 10 Å

and 80 Å

.

13. The barrier structure of claim 1, wherein the thickness of the graded thin film is less than 50 Å

.

14. The barrier structure of claim 1, wherein a concentration of the second metal is about 0% at the lower surface.

15. The barrier structure of claim 14, wherein the concentration of the second impurity is about 50% at the upper surface.

16. The barrier structure of claim 1, further comprising a barrier layer adjacent the lower surface of the graded thin film.

17. The barrier structure of claim 16, wherein the barrier layer comprises the first metal and the impurity.

18. The barrier structure of claim 16, further comprising an electroplating seed layer adjacent the upper surface of the graded thin film.

19. The barrier structure of claim 18, wherein the electroplating seed layer comprises the second metal.

20. The barrier structure of claim 16, wherein each of the barrier layer and the graded thin film lines surfaces of a damascene structure with than about 90% sidewall coverage as compared to field coverage.

21. An integrated circuit comprising:

an insulating layer having field regions on an upper surface and voids formed among the field regions in a damascene scheme; and

a barrier structure lining at least sidewall surfaces of the voids, the barrier layer including a transition region comprising a barrier material and copper, a concentration of copper in the transition region increasing from a lower surface closer to the insulating layer to an upper surface further from the insulating layer, wherein coverage of the sidewall surfaces by the transition region is greater than about 90% of coverage of the field regions by the transition region.

22. The integrated circuit of claim 21, wherein the barrier material comprises a metal nitride.

23. The integrated circuit of claim 21, wherein the barrier structure further comprises a barrier layer formed of the barrier material, the barrier layer being interposed between the lower surface of the transition region and the insulating layer.

24. The integrated circuit of claim 21, wherein the transition region coverage of the sidewall surfaces is greater than about 93% of the transition region coverage of the field regions.

25. The integrated circuit of claim 21, wherein the concentration of copper in the transition region increases generally linearly from the lower surface the upper surface.

26. The integrated circuit of claim 21, wherein the transition region has a thickness between about 7 Å

and 200 Å

.

27. The integrated circuit of claim 21, wherein the transition region has a thickness between about 10 Å

and 80 Å

.

28. A metallization structure in an integrated circuit, comprising:

a copper line; and

a barrier structure covering surfaces of the copper line, the barrier structure comprising a transition region including a barrier compound material mixed with a controlled and varying copper concentration from a maximum copper concentration immediately adjacent the copper line to a minimum copper concentration further from the copper line.

29. The metallization structure of claim 28, wherein the barrier compound material comprises a metal nitride.

30. The metallization structure of claim 29, wherein the metal nitride comprises a metal selected from the group consisting of the titanium, tantalum and tungsten.

31. The metallization structure of claim 28, wherein the barrier structure further comprises a layer of the barrier compound material having substantially no copper therein, the layer of the barrier compound directly overlying the transition region.

32. The metallization structure of claim 28, wherein the transition region has a thickness between about 7 Å

and 200 Å

.

33. The integrated circuit of claim 28, wherein the transition region has a thickness between about 10 Å

and 80 Å

.

34. The integrated circuit of claim 28, wherein the copper composition gradually decreases from the maximum copper concentration to the minimum copper concentration through a thickness of the transition region.

35. The integrated circuit of claim 34, wherein the copper concentration decreases generally linearly.

36. The integrated circuit of claim 28, wherein the barrier structure covers at least sidewall surfaces of the copper line.