Logic architecture for single event upset immunity

• US 6,703,858 B2
• Filed: 07/22/2002
• Issued: 03/09/2004
• Est. Priority Date: 05/12/2000
• Status: Expired due to Term

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Knowles, Kenneth R.
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/201,418
• Publication Number:
  US 20020175713A1
• Time in Patent Office: 596 Days
• Field of Search: 716/1-18, 326/9-15, 327/200, 327/201, 327/210, 327/225, 327/407, 257/369, 257/371, 257/379, 257/380, 365/53, 365/72, 365/156, 365/181, 365/190
• US Class Current: 326/9
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/0075 by using two redundant chains

Abstract

An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to receive input signals spanning redundant input signal sets. A given logic structure within the first logic element may receive specified input signals within a particular input signal set, while an analogous logic structure within the second logic element may receive corresponding input signals within the counterpart input signal set. A radiation induced transient pulse that affects one input signal may affect an output signal asserted by one logic structure; however, since the transient pulse doesn'"'"'t affect a corresponding input signal applied to the analogous logic structure, the dual path logic gate may output at least one correctly valued signal when a transient pulse occurs. The dual to single path converter is coupled to receive signals output by the dual path logic gate. In the event that a transient signal appears at an input of the dual to single path converter, a current path may be interrupted, and a correct output signal value is maintained as a result of stray capacitance present at an output node.

Claims

1. A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a schematic that defines a circuit comprising:

a first logic circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;

a second logic circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second logic circuit logically equivalent to the first logic circuit; and

a conversion circuit having an output, a first input coupled to the output of the first logic circuit, and a second input coupled to the output of the second logic circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

2. A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a circuit layout that defines a circuit comprising:

a first logic circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;

a second logic circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second logic circuit logically equivalent to the first logic circuit; and

a conversion circuit having an output, a first input coupled to the output of the first logic circuit, and a second input coupled to the output of the second logic circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

3. A computer readable medium storing a data structure corresponding to a standard cell, the standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a circuit schematic that defines a circuit comprising:

a first logic circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;

a second logic circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second logic circuit logically equivalent to the first logic circuit; and

a conversion circuit having an output, a first input coupled to the output of the first logic circuit, and a second input coupled to the output of the second logic circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

4. A computer readable medium storing a data structure corresponding to a standard cell, the standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a circuit layout that defines a circuit comprising:

a first logic circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;

a second logic circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second logic circuit logically equivalent to the first logic circuit; and

a conversion circuit having an ouput, a first input coupled to the output of the first logic circuit, and a second input coupled to the output of the second logic circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit,

wherein the first and second versions of the first input signals correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

5. A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a schematic that defines a circuit comprising:

a first inverter circuit having an ouput, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;

a second inverter having an ouput, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal;

a third inverter circuit having an output, a first input coupled to receive a first version of a signal output by the first inverter circuit, and a second input coupled to receive a second version of a signal output by the second inverter circuit;

a fourth inverter circuit having an output, a first input coupled to receive a second version of a signal output by the first inverter circuit, and a second input coupled to receive a first version of a signal output by the second inverter circuit; and

a conversion circuit having an output, a first input coupled to the output of the third inverter circuit, and a second input coupled to the output of the fourth inverter circuit, the conversion circuit comprising a fifth inverter circuit that forms a portion of a current path within a sixth inverter circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse, the first and second versions of the signal output by the first inverter circuit correspond to an identical value in the absence of a transient pulse, and the first and second versions of the signal output by the second inverter circuit correspond to an identical value in the absence of a transient pulse.

6. A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a schematic that defines a circuit comprising:

a first NAND circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal; and

a second NAND circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second NAND circuit logically equivalent to the first NAND circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

7. A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a schematic that defines a circuit comprising:

a first NOR circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal; and

a second NOR circuit having an output a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second NOR circuit logically equivalent to the first NOR circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

8. A circuit, comprising:

a first logic circuit operable to receive first and second input signals, to generate a first output signal having a first logic value in response to the first and second input signals each having a same logic value, and to maintain the first output signal at the first logic value in response to a transient pulse superimposed on one of the first and second input signals; and

a second logic circuit operable to receive the first and second input signals, to generate a second output signal having the first logic value in response to the first and second input signals each having the same logic value, and to maintain the second output signal at the first logic value in response to a transient pulse superimposed on the other of the first and second input signals.

9. The circuit of claim 8 wherein the same logic value comprises a second logic value that is the complement of the first logic value.

10. The circuit of claim 8 wherein the first and second logic circuits respectively comprise first and second inverters.

11. A method, comprising:

generating first and second output signals each having a first logic value in response to first and second input signals each having a same logic value; and

maintaining at least one of the first and second output signals at the first logic value in response to a translent pulse superimposed on one of the first and second input signals.

12. The method of claim 11 wherein the same logic value comprises a second logic value that is the complement of the first logic value.

13. A method, comprising:

generating an output signal having a first logic value in response to first and second input signals each having a same logic value; and

maintaining the output signal at the first logic value in response to a transient pulse superimposed on one of the first and second input signals.

14. The method of claim 13 wherein the same logic value comprises a second logic value that is the complement of the first logic value.

15. A method, comprising:

generating first and second intermediate signals each having a first logic value in response to first and second input signals each having a second logic value;

maintaining at least one of the first and second intermediate signals at the first logic value in response to a transient pulse superimposed on one of the first and second input signals;

generating an output signal having the second logic value in response to the first and second intermediate signals each having the first logic value; and

maintaining the output signal at second logic value in response to a transient pulse superimposed on one of the first and second intermediate signals.

16. The method of claim 15 wherein the second logic value is of the first logic value.

17. A method, comprising:

generating a first output signal having a logic value that is equal to a logical inversion of first and second versions of an input signal;

generating a second output signal having the logic value; and

maintaining at least one of the first and second output signals at the logic value in response to a transient pulse superimposed on one of the versions of the input signal.

18. A method, comprising:

generating a first output signal having a logic value that is equal to a logical NAND of first and second versions of a first input signal and first and second versions of a second input signal;

generating a second output signal having the logic value; and

maintaining at least one of the first and second output signals at the logic value in response to a transient pulse superimposed on one of the versions of the first and second input signals.

19. The method of claim 18 wherein maintaining comprises maintaining at least one of the first and second output signals at the logic value in response to one or more transient pulses superimposed on more than one of the versions of the first and second input signals.

20. A method, comprising:

generating a first output signal having a logic value that is equal to a logical NOR of first and second versions of a first input signal and first and second versions of a second input signal;

generating a second output signal having the logic value; and

maintaining at least one of the first and second output signals at the logic value in response to a transient pulse superimposed on one of the versions of the first and second input signals.

21. The method of claim 20 wherein maintaining comprises maintaining at least one of the first and second output signals at the logic value in response to one or more transient pulses superimposed on mare than one of the versions of the first and second input signals.