I/O block for a programmable interconnect circuit

• US 6,703,860 B1
• Filed: 12/14/2001
• Issued: 03/09/2004
• Est. Priority Date: 12/14/2001
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Agrawal, Om P., Zhu, Jinghui
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/021,844
• Time in Patent Office: 816 Days
• Field of Search: 326/38-41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

A programmable interconnect circuit comprising a plurality of I/O cells arranged into I/O blocks includes a routing structure for each I/O block, wherein each routing structure may programmably route signals between the plurality of I/O cells and the I/O cells within its I/O block. Each I/O cell includes a multiplexer and an I/O circuit associated with a pin of the programmable interconnect circuit. Associated with each I/O block is a control array receiving control signals from its routing structure. An AND array in the control array produces a set of product term control signals for its I/O block from the received control signals.

Claims

1. A programmable interconnect circuit, comprising:

a plurality of input/output (I/O) cells, wherein the I/O cells are arranged into a plurality of N I/O blocks and each I/O cell includes a multiplexer and a register associated with a pin of the programmable interconnect circuit;

a plurality of N routing structures corresponding to the plurality of N I/O blocks, each routing structure configured to receive control and data signals from the plurality of I/O cells and programmably route the control and data signals into a set of control output signals and a set of data output signals;

wherein each I/O block includes a programmable AND array, each programmable AND array being configured to receive the control output signals from its I/O block'"'"'s routing structure and to provide M product term outputs to its I/O block'"'"'s I/O cells, and wherein each I/O block'"'"'s registers may receive data signals from the set of data signals routed by its routing structure.

2. The programmable interconnect circuit of claim 1, wherein the M product term outputs comprise set/reset signals and clock and clock enable signals for controlling the register within each I/O cell.

3. The programmable interconnect circuit of claim 2, wherein each multiplexer for each I/O cell within an I/O block is configured to receive a plurality of signals from its I/O block'"'"'s routing structure'"'"'s set of data output signals and select a multiplexer output signal, and wherein each register of each I/O cell within an I/O block comprises an output register coupled to receive the selected signal from its I/O cell'"'"'s multiplexer and further includes an input register coupled to receive signals from its I/O cell'"'"'s pin and provide the signals to its I/O cell'"'"'s routing structure, the M product terms from each I/O block'"'"'s routing structure further comprising MUX select signals for the I/O block'"'"'s multiplexers.

4. The programmable interconnect circuit of claim 3, wherein each I/O cell further comprises:

an output enable register, wherein each I/O block'"'"'s M product term signals includes an output enable signal for controlling the I/O block'"'"'s output enable registers.

5. The programmable interconnect circuit of claim 4, wherein the programmable AND array is further configured to provide the logical OR of signals from the set of M product terms signals used to form the set/reset and clock/clock enable signals.

6. The programmable interconnect circuit of claim 1, further comprising:

a non-volatile memory for storing configuration data, wherein the configuration data is used to configure the programmable AND array.

7. The programmable interconnect circuit of claim 6, wherein the non-volatile memory is in-system programmable.

8. The programmable interconnect circuit of claim 1, wherein each routing structure in the plurality of routing structures comprises a data-path routing structure and a control-signal routing structure, each data-path routing structure producing its I/O block'"'"'s set of data output signals, each control routing structure producing its I/O block'"'"'s set of control output signals.

9. The programmable interconnect circuit of claim 8, wherein the register in each I/O cell comprises an input register, output register, and an output enable register, the set and reset signals for each input register, output register, and output enable register within an I/O block being derived from the I/O block'"'"'s set of M product terms.

10. The programmable interconnect circuit of claim 9, wherein clock and clock enable signals for each input register, output register, and output enable register within an I/O block'"'"'s I/O cells are derived from the I/O block'"'"'s set of M product terms.

11. The programmable interconnect circuit of claim 10, wherein the same subset of product terms from the set of M product terms are used to derive the clock and clock enable signals for a given I/O cell'"'"'s output register and output enable register.

12. The programmable interconnect circuit of claim 8, wherein each routing structure programmably routes its control and data signals according to the configuration data stored in the non-volatile memory.

13. The programmable interconnect circuit of claim 12, wherein the non-volatile memory is electrically erasable.

14. A programmable interconnect circuit, comprising;

a plurality of input/output (I/O) blocks, each I/O block including a control array and at least two I/O cells, each I/O cell including a multiplexer coupled to an I/O circuit, the control array coupled to the select terminals of each multiplexer and to each I/O circuit; and

a routing structure for receiving input signals and routing them to each I/O block, the routing structure programmable to provide control signals for the control array and data signals for the multiplexers.

15. The programmable interconnect circuit of claim 14, wherein each control array is programmable to route control signals received from the routing structure to each multiplexer and to each I/O circuit.

16. The programmable interconnect circuit of claim 15, wherein each control array includes an AND array.

17. The programmable interconnect circuit of claim 14, wherein each I/O circuit includes one or more registers and a set of control signal paths from the control array to the one or more registers.

18. The programmable interconnect circuit of claim 14, wherein the one or more registers include an input register, an output register, and an output enable register.

19. The programmable interconnect circuit of claim 14, wherein the control array is coupled to the select terminals of at least two multiplexers through a first common set of control signal paths and is coupled to at least two I/O circuits through a second common set of control signal paths.

20. The programmable interconnect circuit of claim 14, including a plurality of routing structures, wherein each muting structure corresponds to an I/O block.

21. A programmable interconnect circuit, comprising:

a plurality of input/output (I/O) blocks, each I/O block including a control array and at least sixteen I/O cells, each I/O cell including a multiplexer coupled to an I/O circuit, the control array coupled to the select terminals of a first set of at least four multiplexers through a first common set of control signal paths, to the select terminals of a second set of at least four multiplexers trough a second common set of control signal paths, to the select terminals of a third set of at least four multiplexers through a third common set of control signal paths, to the select terminals of a fourth set of at least four multiplexers through a fourth common set of control signal paths, and to each I/O circuit; and

a routing structure for receiving input signals and routing them to each I/O block, the routing structure programmable to provide control signals for the control array and data signals for the multiplexers.

22. The programmable interconnect circuit of claim 21, wherein the control array is coupled to a first set of at least four I/O circuits through a fifth common set of control signal paths, to a second set of at least four I/O circuits through a sixth common set of control signal paths, to a third set of at least four I/O circuits through a seventh common set of control signal paths, and to a fourth set of a least four I/O circuits through an eighth common set of control signal paths.

23. A programmable semiconductor device, comprising:

a plurality of input/output I/O cells each including an output multiplexer coupled to an I/O circuit, the I/O circuit including an input register, an output register, and an output enable register, the input register coupled to an I/O pin and operable to store an input signal received at the pin, the output register coupled to the multiplexer and operable to store an output signal received from the multiplexer for the I/O pin, and the output enable register coupled to an output buffer that is coupled between the output register and the I/O pin, the output enable register operable to control the output buffer to provide an output signal on the I/O pin;

a routing structure for receiving input signals from the I/O pins and routing them to the I/O cells, the routing structure programmable to provide control signals for the registers of the I/O circuit and data signals for the multiplexer within each I/O cell.

24. The programmable semiconductor device of claim 23, wherein the I/O circuit for each I/O cell includes a feedback multiplexer having its output terminal coupled to the routing structure and its input terminals coupled to the output terminal of the output multiplexer, the output register, the I/O pin, and the input register.

25. The programmable semiconductor device of claim 23, wherein the I/O circuit for each I/O cell includes a feedback multiplexer operable to feed the output signal of the output multiplexer back to the routing structure, and wherein the routing structure is programmable to route the fed back output signals from a first set of the output multiplexers to the input terminals of another one of the output multiplexers, thereby forming a wider multiplexer.

26. The programmable semiconductor device of claim 23, wherein the I/O circuit for each I/O cell includes an output register bypass multiplexer having an output coupled to the output buffer and an input selected from the output signal of the output multiplexer or the stored output signal of the output register.

27. The programmable semiconductor device of claim 26, wherein the output register bypass multiplexer is operable to select as an input signal from among the output signal of the output multiplexer, the inverse of the output signal, the stored output signal of the output register, and the inverse of the stored output signal.

28. The programmable semiconductor device of claim 23, wherein the I/O circuit for each I/O cell includes an output enable register bypass multiplexer coupled to the output buffer and operable to select between the output signal of the output multiplexer and the stored output signal of the output enable register.

29. The programmable semiconductor device of claim 28, wherein the output enable register bypass multiplexer is operable to select among the output signal of the output multiplexer, the inverse of the output signal, the stored output signal of the output enable register, and the inverse of the stored output enable signal.

30. The programmable semiconductor device of claim 23, wherein the I/O cells are arranged into I/O blocks of multiple I/O cells per block, and the routing structure is coupled to an I/O block through common control signal paths shared by the I/O cells within the I/O block.

31. The programmable semiconductor device of claim 30, wherein each I/O block includes a control array, the control array coupled to the output multiplexer and input register, output register, and output enable register of each I/O cell within its I/O block and programmable to provide control signals thereto derived from control signals received by the control array from the routing structure.

32. The programmable semiconductor device of claim 31, wherein the I/O cells within each I/O block are coupled to global signal paths to receive global signals specific to the I/O cells.

33. The programmable semiconductor device of claim 32, wherein the global signals comprise clock signals, clock enable signals, output enable signals, or output multiplexer select signals.

34. The programmable semiconductor device of claim 33, wherein the common control signals comprise clock product term signals, clock enable product term signals, output enable product term signals, or set/reset product term signals.

35. The programmable semiconductor device of claim 34, wherein each of the input register, output register, and output enable register within an I/O cell is coupled to receive global signals and common control signals.

36. The programmable semiconductor device of claim 35, wherein the output register and output enable register are coupled to receive the same global clock and clock enable signals and clock product term and clock enable product term signals.

37. The programmable semiconductor device of claim 34, wherein each I/O cell includes a demultiplexer coupled at its input terminal to a source of a register set/reset signal and coupled at its output terminals to set and reset terminals of at least one of the input register, output register, and output enable register within the I/O cell, the demultiplexer operable to switch a register set/reset signal received from the source between the set and reset terminals.

38. The programmable semiconductor device of claim 37, wherein the output register and output enable register are coupled to receive the same register set/reset signal.

39. The programmable interconnect circuit of claim 25 including:

a plurality of data signal paths coupled to input terminals of the output multiplexer; and

a plurality of look-up table (LUT) multiplexers corresponding to the plurality of data signal paths, each LUT multiplexer having its output terminal coupled to its corresponding data signal path, one of its input terminals coupled to a source of high impedance, another of its input terminals coupled to a source of a logic 0 signal, and another of its input terminals coupled to a source of a logic 1 signal,

the LUT multiplexers operable to provide, in combination with the output multiplexer, a look-up table for the I/O cell with the logic 0 or logic 1 source selected as the source of the output signal for each LUT multiplexer.