Serial interface for an analog to digital converter and a converter including such an interface

• US 6,703,961 B2
• Filed: 04/23/2002
• Issued: 03/09/2004
• Est. Priority Date: 04/23/2002
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Mueck, Michael, Guery, Alain Valentin, Laing, David Gerrard
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US10/128,033
• Publication Number:
  US 20030197635A1
• Time in Patent Office: 686 Days
• Field of Search: 341/161, 341/155, 341/122, 341/123, 341/162
• US Class Current: 341/161
• CPC Class Codes: G06F 3/05 Digital input using the sampling of an analogue quantity at regular intervals of time , input from a/d converter or output to d/a converter

Abstract

An analog to digital converter is provided which has a compact serial interface utilising only four pins to define chained and non chained modes of operation. Further more the interface also allows the converter to be configured to indicate immediately that the conversion has been completed. Another variant of the invention enables an analog to digital converter to be provided having only a 3 pin serial interface.

Claims

1. An analog to digital converter comprising a converter section and an interface section, the interface section having a first input and an output from which a digital word representing the result of a conversion can be read, and wherein in a first mode of operation the output is placed into a predetermined output state to signal that the conversion has been completed, and in which the first mode is selected by placing the first input into a first predetermined state before the conversion is complete.

2. An analog to digital converter as claimed in claim 1, in which the first input acts in the first predetermined state as a device select pin for signalling to the analog to digital converter that it is to assert an output signal at its output.

3. An analog to digital converter as claimed in claim 2, in which the output is in a high impedance condition when the device select pin is not in the first predetermined state.

4. An analog to digital converter as claimed in claim 2, in which the first input acts as a start of convert signal.

5. An analog to digital converter as claimed in claim 2, in which a transition of the first input from the first predetermined state to a second predetermined state initiates an analog to digital conversion.

6. An analog to digital converter as claimed in claim 2, further including a second input for initiating a conversion.

7. An analog to digital converter as claimed in claim 6, in which a conversion is started in response to a predetermined transition of a signal applied to the second input.

8. An analog to digital converter as claimed in claim 7, in which the conversion is initiated when the second input goes from a “

low”

to a “

high”

.

9. An analog to digital converter as claimed in claim 6, in which the converter is reset by a specific combination of signals on the first and second inputs.

10. An analog to digital converter as claimed in claim 9, in which the converter is reset by taking the first and second inputs low concurrently.

11. An analog to digital converter as claimed in claim 1, further including a serial clock input, and in which data is read out from the output in synchronism with clock signals applied to the serial clock.

12. An analog to digital converter as claimed in claim 1, in which the first predetermined output state is a “

low”

.

13. An analog to digital converter as claimed in claim 1, in which in a second mode of operation the output of the analog to digital converter remains in a high impedance state until such time as the converter is instructed to output its data upon receipt of a device select signal.

14. An analog to digital converter as claimed in claim 1, in which the analog to digital converter further comprises a second input and a serial clock input, and wherein following the initiation of a conversion by applying a start of convert signal to the second input the converter examines the status of its first input and the serial clock input, and if the first input is in the first predetermined state and the serial clock input is in a first predetermined serial clock state, then the analog to digital converter enters a third mode where the output is asserted to a third mode predetermined output state to signal that a conversion has been completed when the conversion has been completed and the first input is in a second predetermined state.

15. An analog to digital converter as claimed in claim 14 wherein, in the third mode, the first input further functions as a serial data input, and wherein a plurality of M converters can be connected in series with the output of an Nth converter being connected to the serial data input of an N+1th converter, and the output of the N+1th converter only signals that a conversion is completed when it and all preceding analog to digital converters have completed their conversions, and where N is an integer in the range 1 to (M−

1).

16. An analog to digital converter as claimed in claim 14, wherein the a digital interface thereof only has four connections for interfacing the analog to digital converter with other devices.

17. An analog to digital converter as claimed in claim 14, in which the first input further functions as a serial data input such that data appearing at the serial data input is shifted into a shift register within the analog to digital converter for subsequent output.

18. An analog to digital converter as claimed in claim 14 in which the analog to digital converter is further operable in a fourth mode in which the converter is operable in a chain of serially connected converters but the converter does not assert a ready signal when the end of conversion is received.

19. An analog to digital converter as claimed in claim 14, in which the third mode is a “

chain, ready”

mode in which the converter is connected in series with other converters and asserts an output when it and any preceding converters have completed their conversions irrespective of whether the converter is operable in a second mode.

20. An analog to digital converter as claimed in claim 1, in which the analog to digital converter further comprises a second input and a serial clock input, and wherein following the initiation of a conversion by applying a start of convert signal to the second input, the converter examines the status of its first input and the serial clock input, and if the first input is in the first predetermined state and the serial clock input is in a second predetermined serial clock state, then the analog to digital converter enters a fourth mode where it clocks data at the first input into a shift register for subsequent output and where the output does not assert a signal to indicate that a conversion is complete.

21. An analog to digital converter as claimed in claim 1, in which the analog to digital converter can be programmed by truncating a data read instruction cycle before all of the conversion result has been output.

22. An analog to digital converter as claimed in claim 1, wherein the first input is a serial data input and wherein the analog to digital converter further comprises a clock input and a convert input for initiating a conversion, and the analog to digital converter is programmable by inputting a control word via the serial data input.

23. An analog to digital converter comprising a converter section and an interface section, the interface section having a first input and an output for outputting the result of a conversion, and wherein in a first mode the output is asserted to a first predetermined state to indicate that the conversion has been completed when the conversion has been completed and the first input is at a first predetermined input state.

24. An analog to digital converter as claimed in claim 23, in which the converter further includes a clock input, and the conversion result is output in response to transitions of a clock signal at the clock input between a first and a second predetermined state.

25. An analog to digital converter as claimed in claim 24, where the converter further includes a convert input which initiates a conversion.

26. An analog to digital converter as claimed in claim 25, where the digital interface only has four connections.

27. An analog to digital converter as claimed in claim 25, in which the first mode is selected by examining the status of the first input and the clock input following the initiation of a conversion, and a predetermined combination of signals on these inputs indicates that the first mode is to be selected.

28. An analog to digital converter as claimed in claim 27, in which the first mode is selected when the first input is low and the clock signal is high.

29. A converter as claimed in claim 25, in which a reset condition is defined by the first input being in a predetermined state and the convert input being in a predetermined state.

30. A converter as claimed in claim 29, in which the reset condition is defined by the first input and the convert input being in the same state.

31. A converter as claimed in claim 30, in which the reset condition is defined by the first input and the convert input both being in a logic “

0”

state.

32. A converter as claimed in claim 25, in which a time delay is inserted in the first input signal path within the converter such that a record of the first input status can be latched in response to a transition of the convert input.

33. A converter as claimed in claim 24, in which the converter includes a mode controller which examines the status of the clock input to determine whether a ready signal is to be given when the conversion has been completed.

34. A converter as claimed in claim 33, in which a “

signal when ready”

mode in which the converter outputs a signal to indicate when it has completed a conversion is selected by the clock input being high when a convert signal is asserted.

35. An analog to digital converter as claimed in claim 23, wherein, in the first mode, a plurality of converters can be connected in series with the output of an Nth converter being connected to the first input of an N+1th converter, and the output of the N+1th converter only signals that the conversion is complete when it and all preceding converters have competed their conversions, where the converters are numbered 1 to N+1.

36. An analog to digital converter as claimed in claim 35, in which while reading data in the first mode, the converters operate in a chained manner such that data appearing at the first input is shifted into a shift register within the converter for subsequent output.

37. An analog converter as claimed in claim 23, in which the converter is operable in a second mode of operation, in which the first input is in a second predetermined state, and the converters are connected in a chain but the converters do not assert a ready signal when the end of the conversion is achieved.

38. An analog to digital converter as claimed in claim 37, in which the analog to digital converter further includes a clock input and a convert input, and the status of the first input and the clock signal following initiation of a conversion is examined, and the second mode is selected in response to a predetermined combination of signals on these inputs.

39. An analog to digital converter as claimed in claim 38, in which the second mode is selected when the first input is low and the clock signal is low.

40. A serial interface for a task performing device wherein the device will complete the task after an unspecified duration but within a predetermined maximum duration, and wherein the serial interface comprises a serial clock input, a serial output and a control input and the interface is arranged such that a first transition of the control input initiates the task, and a further transition of the control input prior to completion of the task instructs the serial interface to assert a signal on the serial output once the task has been completed.

41. A serial interface for a task performing device as claimed in claim 40, in which the serial output can assume a high impedance state, and in which during performance of the task the serial output assumes a high impedance state, and once the task has been completed the serial output exits from the high impedance to assert a signal to indicate that the task has been completed.

42. A serial interface for a task performing device as claimed in claim 40, in which the serial output goes “

low”

to signal that the task has been completed.

43. A serial interface for a task performing device as claimed in claim 40,in which completion of the task results in the production of digital data, and the data can be output via the serial output in response to a pulse train applied to the serial clock input.

44. A serial interface for a task performing device as claimed in claim 43, in which once the data has been read out the serial output is placed in a predetermined state.

45. A serial interface for a task performing device as claimed in claim 43, in which once the serial data has been read out the serial output is placed in a high impedance state.

46. A serial interface for a task performing device as claimed in claim 44, wherein in the absence of a further transition of the control input before the completion of the task the serial output assumes a high impedance condition until such time as a transition on the control input occurs.

47. A serial interface for a task performing device as claimed in claim 46, in which in response to the transition of the control input after the completion of the task, data is read out from the serial output, with the first bit of the data being set up on the serial output in response to the transition.

48. A serial interface for a task performing device as claimed in claim 40, in which the first transition takes the control input from low to high.

49. A serial interface for a task performing device as claimed in claim 40, in which the second transition takes the control pin-input from high to low.

50. A serial interface for a task performing device as claimed in claim 40, wherein the interface further comprises a second input and the interface is operable in a further mode of operation where a signal on the output is only asserted when both the device has completed its task and the second input is at a predetermined state.

51. An analog to digital converter including a serial interface as claimed in claim 40.