FeRAM memory and method for manufacturing it

• US 6,704,219 B2
• Filed: 07/01/2002
• Issued: 03/09/2004
• Est. Priority Date: 06/29/2001
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Nagel, Nicolas, Bruchhaus, Rainer, Hartner, Walter, Mikolajick, Thomas, Enders, Gerhard, Krönke, Matthias, Röhner, Michael
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US10/186,645
• Publication Number:
  US 20030053346A1
• Time in Patent Office: 617 Days
• Field of Search: 365/145, 365/149, 365/117, 365/173
• US Class Current: 365/145
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.

Claims

1. A FeRAM memory, comprising:

at least one of a semiconductor substrate, a passivation region and a surface region formed with a CMOS structure; and

a capacitor configuration having a multiplicity of capacitor devices used as storage elements disposed in a region of said at least one of said semiconductor substrate, said passivation region, and said surface region, at least some of said capacitor devices being formed with a multiplicity of individual capacitors connected in parallel with one another, said individual capacitors having one of ferroelectric and paraelectric dielectric regions with different coercitive voltages to provide each of said capacitor devices with a multiplicity of storage states.

2. The FeRAM memory according to claim 1, wherein each of said capacitor devices has a first electrode device, a second electrode device, and a dielectric disposed between said first electrode device and said second electrode device.

3. The FeRAM memory according to claim 2, wherein at least some of said first and second electrode devices have electrodes respectively electrically connected to one another to thereby form said multiplicity of individual capacitors connected in parallel with one another.

4. The FeRAM memory according to claim 3, wherein at least some of said electrodes connected to one another are identified with one another as at least one of:

an electrically conductive one-part region; and

an electrically conductive one-piece region.

5. The FeRAM memory according to claim 3, wherein at least some of said capacitor devices have a first contact element and second contact element and are in contact:

with a first electrode device of a first directly spatially adjacent one of said capacitor devices by a respective one of said first electrode devices through said first contact element; and

with a second electrode device of a second directly spatially adjacent one of said capacitor devices by a respective one of said second electrode devices through said second contact element,

to form a capacitor configuration having at least one of a partially connected structure and a chain structure.

6. The FeRAM memory according to claim 1, wherein at least some of said capacitor devices are in a stack structure.

7. A method for manufacturing a FeRAM memory, which comprises:

forming at least one of a semiconductor substrate, a passivation region, and a surface region with a CMOS structure; and

forming a capacitor configuration of a multiplicity of capacitor devices used as storage elements in a region of the at least one of the semiconductor substrate, the passivation region, and the surface region, at least some of the capacitor devices being formed with a multiplicity of individual capacitors connected in parallel with one another, the individual capacitors being formed with one of ferroelectric and paraelectric dielectric regions with different coercitive voltages, and, as a result, each capacitor device is formed with a multiplicity of storage states.

8. The method according to claim 7, which further comprises providing, for each of the capacitor devices, a first electrode device, a second electrode device, and a dielectric formed between the first electrode device and the second electrode device.

9. The method according to claim 8, which further comprises forming at least some of the first and second electrode devices with a multiplicity of electrodes respectively electrically connected to one another, and, as a result, forming the multiplicity of individual capacitors connected in parallel with one another.

10. The method according to claim 9, which further comprises identifying at least some of the respective multiplicity of electrodes connected to one another as at least one of an electrically conductive one-part region and an electrically conductive one-piece region.

11. The method according to claim 9, which further comprises forming a capacitor configuration with at least one of a partially connected structure and a chain structure by:

connecting a respective first electrode device of at least some of the capacitor devices to a first electrode device of a first directly spatially adjacent one of the capacitor devices through a first contact element; and

connecting a respective second electrode device to a second electrode device of a second directly spatially adjacent one of the capacitor devices through a second contact element.

12. The method according to claim 7, which further comprises configuring at least some of the capacitor devices in a stack structure.

13. The method according to claim 7, which further comprises one of at least partially covering and at least partially embedding, in a two-dimensional method covering at least a substantial area of one of the semiconductor substrate and the surface region, the CMOS structure and one of a horizontally extending semiconductor substrate and the surface region with at least a first upper and laterally extending passivation region of an electrically insulating material, said first upper and laterally extending passivation region having a planar surface region.

14. The method according to claim 13, which further comprises forming, with a common and selective etching process, first cutouts in defined first and second locations in the first upper passivation region.

15. The method according to claim 14, which further comprises:

providing selector transistor devices of the CMOS structure above source/drain regions in surface regions of the semiconductor substrate; and

selecting the selector transistor devices as the defined first and second locations.

16. The method according to claim 15, which further comprises vertically forming the first cutouts at least to a given extent as far as a level of surface regions of the source/drain regions of the selector transmitter devices.

17. The method according to claim 16, which further comprises forming a first material region of an electrically conductive material on a surface region of the first passivation region by two-dimensional deposition in a conformal form covering substantially all of the area and filling the respective first cutout as far as the level of the surface region of the source/drain regions and subsequently polishing to a level of the surface region of the first passivation region.

18. The method according to claim 16, which further comprises forming a first material region of an electrically conductive material on a surface region of the first passivation region by two-dimensional deposition in a conformal form covering a given area and filling the respective first cutout as far as the level of the surface region of the source/drain regions and subsequently polishing to a level of the surface region of the first passivation region.

19. The method according to claim 17, which further comprises depositing at least a second material region for first electrodes for the first electrode devices from at least one of the group consisting of an electrically conductive material, a metal, and a metal oxide in a two-dimensional, conformal fashion over a given area with a planar surface region to form first and second plug regions making contact with the capacitor devices and the CMOS structure.

20. The method according to claim 19, which further comprises constructing the first and second plug regions identically.

21. The method according to claim 20, which further comprises depositing a third material region for first dielectric regions of the dielectric in a form of one of the group consisting of a ferroelectric and a paraelectric in a two-dimensional, conformal fashion over a given area with planar surface regions on a surface region of the second material region.

22. The method according to claim 19, which further comprises structuring at least the second material region for the first electrodes of the first electrode device by an anisotropic etching process and with cutouts in the region of the second defined locations, and, as a result, forming pairs of connected first electrodes, electrically insulated from one another and from the second plug regions, of the first electrode devices in respective common electrical contact with the first plug regions.

23. The method according to claim 21, which further comprises one of forming and patterning the second and the third material regions together in a sequence selected from the group consisting of a common process sequence and a cascaded process sequence.

24. The method according to claim 23, which further comprises forming a second passivation region of an electrically insulating material in a two-dimensional, conformal fashion over a given area, surface regions of at least one region selected from the group consisting of the second plug regions, the first dielectric regions, the first electrodes, the first electrode device, and the first passivation region and parts of the at least one region being one of embedded and covered as far as a level of a surface region of the first dielectric region by subsequent polishing with a stop at the level of the surface region of the first dielectric region.

25. The method according to claim 24, which further comprises forming second cutouts at the defined second locations by selective etching back and, in the process, removing material of the second passivation region as far as the level of the surface regions of the second plug regions to respectively expose the surface region of the sccond plug region.

26. The method according to claim 25, which further comprises depositing a fourth material region for first electrodes of the second electrode device selected from the group consisting of an electrically conductive material, a metal, and a metal oxide in a two-dimensional, conformal fashion over a given area with a planar surface region.

27. The method according to claim 26, which further comprises:

patterning the fourth material region for the first electrodes of the second electrode devices with an anisotropic etching process and with cutouts in a region of the first defined locations; and

forming pairs of connected first electrodes, insulated from one another and from the first plug regions, of the second electrode device in respective common electrical contact with the second plug regions.

28. The method according to claim 27, which further comprises depositing a fifth material region for a second dielectric region for the dielectric in the form of one of a ferroelectric and a paraelectric in a two-dimensional, conformal fashion over a given area with a planar surface region on a surface region of the fourth material region.

29. The method according to claim 28, which further comprises forming a third passivation region of a substantially electrically insulating material in a two-dimensional, conformal fashion over a given area, surface regions of at least one region selected from the group consisting of the first electrodes of the second electrode devices, the second dielectric regions of the dielectric, and the second passivation region and parts of the at least one region being one of embedded and covered as far as a level of surface regions of the second dielectric regions of the dielectric by subsequent polishing with a stop at the level of the surface regions of the second dielectric regions of the dielectric.

30. The method according to claim 29, which further comprises forming third cutouts at the defined first locations by selective etching back, and, in the process:

eroding the material of the third passivation region as far as the level of the surface regions of the first electrodes of the first electrode devices to at least partially expose the surface region of the first electrodes of the first electrode devices; and

one of leaving and forming spacer elements for electrically insulating the first electrodes of the first electrode devices in adjacent peripheral regions of the first electrodes of the second electrode devices.

31. The method according to claim 30, which further comprises vertically forming the third cutouts at least partially as far as the level of surface regions of the first electrodes of the first electrode device.

32. The method according to claim 31, which further comprises forming a sixth material region of an electrically conductive material in a two-dimensional, conformal fashion to cover a given area and to fill the third cutout respectively as far as the level of the surface regions of the first electrodes of the first electrode devices;

and forming intermediate plug regions in substantially electrical contact with the first electrodes of the first electrode devices and with the first plug regions by polishing with a stop at the level of the surface regions of the second dielectric regions of the dielectric.

33. The method according to claim 32, which further comprises one of forming and depositing a seventh material region for second electrodes of the first electrode device from one of the group consisting of an electrically conductive material, a metal, and a metal oxide in a two-dimensional, conformal fashion over a given area with a planar surface region.

34. The method according to claim 33, which further comprises patterning the seventh material region for the second electrodes of the first electrode device with an anisotropic etching process and with cutouts in a region of the second defined locations, and, as a result, forming pairs of connected second electrodes, electrically insulated from one another and from the first electrodes of the second electrode device, of the first electrode device in respective substantially common contact with the extension plug region.

35. The method according to claim 34, which further comprises forming a fourth passivation region of an electrically insulating material in a two-dimensional, conformal fashion over a given area, surface regions of at least one region selected from the group consisting of the second electrodes of the first electrode device and the fourth passivation region being one of embedded and covered with a planar surface region.

36. The method according to claim 7, which further comprises forming the multiplicity of capacitor devices one on top of another.