Frequency acquisition rate control in phase lock loop circuits

• US 6,704,381 B1
• Filed: 09/17/1999
• Issued: 03/09/2004
• Est. Priority Date: 09/17/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moyal, Nathan Y., Williams, Bertrand J., Marlett, Mark, Meyers, Steve
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): ODOM, CURTIS B
• Application Number:
  US09/398,956
• Time in Patent Office: 1,635 Days
• Field of Search: 375/374, 375/376, 327/153, 327/159, 713/503, 455/73
• US Class Current: 375/374
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first reference signal in response to a pump-up signal and (ii) a second reference signal in response to a pump-down signal. The second circuit may be configured to generate (a) a first control signal in response to (i) the pump-up signal and (ii) the second reference signal and (b) a second control signal in response to (i) the pump-down signal and (ii) the first reference signal.

Claims

1. An apparatus comprising:

a first circuit configured to generate (i) a first reference signal in response to a pump-up signal and (ii) a second reference signal in response to a pump-down signal; and

a second circuit configured to generate (a) a first control signal in response to (i) said pump-up signal and (ii) said second reference signal and (b) a second control signal in response to (i) said pump-down signal and (ii) said first reference signal.

2. The circuit according to claim 1, wherein said first circuit further comprises:

a first generator circuit configured to generate said first reference signal as a first reference pulse width signal; and

a second generator circuit configured to generate said second reference signal as a second reference pulse width signal.

3. The apparatus according to claim 1, wherein said first circuit comprises a pulse generator circuit.

4. The apparatus according to claim 1, wherein said second circuit comprises a pulse comparator circuit.

5. The apparatus according to claim 1, wherein said apparatus comprises a pulse width limiting circuit configured to limit the pulse width of signals generated by a phase and/or frequency detector.

6. The apparatus according to claim 5, wherein said pulse width limitation circuit is configured to limit the pulse width to a predetermined value.

7. The apparatus according to claim 1, wherein said apparatus is implemented in a phase locked loop (PLL).

8. The apparatus according to claim 5, wherein said predetermined value is configured in response to a voltage control signal.

9. The apparatus according to claim 8, wherein said voltage control signal is generated by a charge pump and/or loop filter.

10. The apparatus according to claim 5, wherein said predetermined value is configured in response to settings of a feedback divider.

11. The apparatus according to claim 1, wherein said first control signal is presented to a first multiplexer and said second control signal is presented to a second multiplexer.

12. The apparatus according to claim 11, wherein:

said first multiplexer selects between said pump-up signal and said first control signal; and

said second multiplexer selects between said pump-down signal and said second control signal.

13. The apparatus according to claim 12, wherein said first and second multiplexers are configured to respond to an external pulse width control signal.

14. The apparatus according to claim 12, wherein said first and second multiplexers are configured to respond to a signal from a lock detect or other logic circuit.

15. The apparatus according to claim 11, wherein:

said first multiplexer selects between said first control signal and a first digital signal; and

said second multiplexer selects between said second control signal and said first digital signal.

16. The apparatus according to claim 15, wherein said first and second multiplexers are configured to respond to a reference clock signal.

17. The apparatus according to claim 16, wherein said first and second multiplexers are configured to respond to a signal from a feedback divider.

18. An apparatus comprising:

means for generating (i) a first reference signal in response to a pump-up signal and (ii) a second reference signal in response to a pump-down signal; and

means for generating (a) a first control signal in response to (i) said pump-up signal and (ii) said second reference signal and (b) a second control signal in response to (i) said pump-down signal and (ii) said first reference signal.

19. A method for controlling the rate of frequency acquisition of a phase lock loop comprising the steps of:

(A) generating a first reference signal in response to a pump-up signal;

(B) generating a second reference signal in response to a pump-down signal;

(C) generating a first control signal in response to (i) said pump-up signal and (ii) said second reference signal; and

(D) generating a second control signal in response to (i) said pump-down signal and (ii) said first reference signal.