Sample and hold type fractional-N frequency synthesizer

• US 6,704,383 B2
• Filed: 08/29/2001
• Issued: 03/09/2004
• Est. Priority Date: 03/20/2001
• Status: Expired due to Term

• Current Assignee: GCT Semiconductor Incorporated
• Original Assignee: GCT Semiconductor Incorporated
• Inventors: Huh, Hyungki, Lee, Jeongwoo, Lee, Kang Yoon, Lee, Kyeongho, Park, Joonbae, Koo, Yido, Song, Eunseok
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US09/940,808
• Publication Number:
  US 20020136342A1
• Time in Patent Office: 923 Days
• Field of Search: 375/371, 375/373, 375/374, 375/375, 375/326, 375/327, 375/376, 327/146-150, 327/155-159
• US Class Current: 375/376
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.

Claims

1. A phase locked loop, comprising:

a first phase detector that receives an input signal and a first divided signal to output a first comparison signal;

a second phase detector that receives the input signal and a second divided signal to output a second comparison signal;

a sample-and-hold circuit that receives the first and second comparison signals and generates an output signal responsive to the comparison signals;

a voltage-controlled oscillator that receives the output signal from the sample-and-hold circuit and generates a prescribed frequency signal; and

a modulus divider that receives the prescribed frequency signal and generates the first and second divided signals having a prescribed phase relationship.

2. The phase-locked loop of claim 1, further comprising a plurality of parallel switches operated by a control line, wherein each of the switches couple a corresponding one of a plurality of charge pumps to a selected one of the first and second comparison signals, depending on the position of said each switch.

3. The phase-locked loop of claim 2, wherein each of the charge pumps performs one of sourcing and sinking a prescribed amount of current to the sample-and-hold circuit.

4. The phase-locked loop of claim 1, wherein the first phase detector comprises:

a phase detector portion with a first output port and a second output port; and

a charge pump portion having a plurality of charge pump stages.

5. The phase-locked loop of claim 4, wherein each of the charge pump stages comprises:

a first current source and a first switch coupled in series between a first prescribed voltage and a charge pump output terminal;

a second current source and a second switch coupled in series between a second prescribed voltage and the charge pump output terminal;

a first logic gate with a first input coupled to the first output port of the phase detector portion, a second input that receives a control signal and an output port coupled to the first switch; and

a second logic gate with a first input coupled to the second output port of the phase detector portion, a second input that receives the control signal and an output port coupled to the second switch.

6. The phase-locked loop of claim 5, wherein the first and second logic gates are AND gates, wherein an output of the first and second AND gates select one of the first and second switches to couple the charge pump output terminal to one of the first and second current sources.

7. The phase-locked loop of claim 1, further comprising a detection circuit coupled to adjust a reference voltage in the sample-and-hold circuit.

8. The phase-locked loop of claim 1, wherein the sample-and-hold circuit comprises:

a first switch and a first capacitor coupled at a first node in series between first and second prescribed reference voltages, wherein the first node is coupled to receive the first and second comparison signals;

a second capacitor coupled between the second reference voltage and a second node; and

a second switch coupled between the first and second nodes.

9. The phase-locked loop of claim 8, further comprising a detection circuit that sets the first prescribed reference voltage.

10. The phase-locked loop of claim 9, wherein the detection circuit comprises:

a lock detector that receives the comparison signals from the first and second phase detectors; and

a digital-to-analog converter that adjusts a voltage level of the first prescribed reference voltage responsive to a control signal from the lock detector.

11. The phase-locked loop of claim 9, wherein the detection circuit comprises:

an analog-to-digital converter that receives the output of the sample-and-hold circuit; and

a digital-to-analog converter that adjusts a voltage level of the first prescribed reference voltage responsive to a control signal from the analog-to-digital converter.

12. The phase-locked loop of claim 9, wherein the detection circuit comprises:

a lock detector that receives the output signal from the sample-and-hold circuit; and

a digital-to-analog converter that adjusts a voltage level of the first prescribed reference voltage responsive to a control signal from the lock detector.

13. The phase-locked loop of claim 1, wherein the first and second divided signals have the same frequency, wherein the first and second divided signals differ in phase by a period of the clock signal, and wherein the first phase detector and the second phase detector are of the same design.

14. The phase-locked loop of claim 1, wherein the modulus divider comprises:

a first logic gate;

a second logic gate that receives a control signal;

a first flip-flop coupled to receive an output signal of the first logic gate and a clock signal from the output port of the voltage-controlled oscillator;

a second flip-flop gate coupled to receive an output signal of the first flip-flop, wherein the first and second logic gates receive an output signal of the second flip-flop; and

a third flip-flop coupled to receive an output signal from the second logic gate, wherein the first, second and third flip-flops receive the prescribed frequency signal as a clock signal, wherein an output signal of the third flip-flop is received by the first logic gate, and wherein the output signals of the first and second flip-flops are the divided signals.

15. The phase-locked-loop of claim 1, wherein said prescribed phase relationship corresponds to a predetermined phase difference.

16. The phase-locked-loop of claim 15, wherein said predetermined phase difference corresponds to one period of a voltage-controlled oscillator frequency.

17. A fractional-N frequency synthesizer for a mobile terminal, comprising:

a phase detector circuit that comprises,

a first phase detector having a first input port coupled to receive a reference signal, a second input port, a third input port and an output port, and

a second phase detector having a first input port coupled to receive the reference signal, a second input port, a third input port and an output port;

a sample-and-hold circuit having a first input port coupled to the output ports of the first and second phase detectors and an output port;

a voltage-controlled oscillator having an input port coupled to the output port of the sample-and-hold circuit and transmitting a prescribed frequency signal at an output port;

a programmable modulus divider having a first output port coupled to the second input port of the first phase detector to transmit a first divided signal, a second output port coupled to the second input port of the second phase detector to transmit a second divided signal, a first input port coupled to the output port of the voltage-controlled oscillator and a second input port; and

an accumulator having a first output port coupled to the second input port of the programmable modulus divider and a second output port coupled to the third input ports of the phase detectors.

18. The fractional-N frequency synthesizer of claim 17, wherein the mobile terminal is one of a cellular phone, a personal digital assistant, a digital audio player, an Internet appliance, a remote control device and a laptop computer.

19. The fractional-N frequency synthesizer of claim 17, further comprising a plurality of switches operated by a control line, wherein each of the switches couple a corresponding one of a plurality of charge pumps to the output port of a selected one of the first phase detector and the second phase detector according to a control signal from the accumulator.

20. The fractional-N frequency synthesizer of claim 17, wherein the first phase detector comprises:

a phase detector portion with a first output port and a second output port; and

a charge pump portion having a plurality of charge pump stages.

21. The fractional-N frequency synthesizer of claim 20, wherein each of the charge pump stages comprises:

a first current source and a first switch coupled in series between a first prescribed voltage and a charge pump output terminal;

a second current source and a second switch coupled in series between a second prescribed voltage and the charge pump output terminal;

a first logic gate with a first input port coupled to the first output port of the phase detector portion, a second input that receives a control signal and an output port coupled to the first switch; and

a second logic gate with a first input coupled to the second output port of the phase detector portion, a second input that receives the control signal and an output port coupled to the second switch.

22. The phase-locked loop of claim 17, wherein the sample-and-hold circuit comprises:

a first switch and a first capacitor coupled at a first node in series between first and second prescribed reference voltages, wherein the first node is coupled to receive first and second comparison signals from the output ports of the phase detectors;

a second capacitor coupled between the second reference voltage and a second node; and

a second switch coupled between the first and second nodes.

23. The phase-locked loop of claim 22, further comprising a detection circuit that sets the first prescribed reference voltage.

24. The phase-locked loop of claim 23, wherein the detection circuit comprises:

a lock detector that receives the comparison signals from the first and second phase detectors; and

a digital-to-analog converter that adjusts a voltage level of the first prescribed reference voltage responsive to a control signal from the lock detector.

25. The phase-locked loop of claim 23, wherein the detection circuit comprises:

an analog-to-digital converter that inputs an output signal of the sample-and-hold circuit; and

a digital-to-analog converter that adjusts a voltage level of the first prescribed reference voltage responsive to a control signal from the analog-to-digital converter.

26. The fractional-N frequency synthesizer of claim 17, wherein the programmable modulus divider comprises:

a first logic gate;

a second logic gate that receives a control signal;

a first flip-flop coupled to receive an output signal of the first logic gate and a clock signal from the output port of the voltage-controlled oscillator;

a second flip-flop gate coupled to receive an output signal of the first flip-flop, wherein the first and second logic gates receive an output signal of the second flip-flop;

a third flip-flop coupled to receive an output signal from the second logic gate, wherein the first, second and third flip-flops receive the prescribed frequency signal as a clock signal, wherein an output signal of the third flip-flop is received by the first logic gate, and wherein the output signals of the first and second flip-flops are the divided signals.

27. The fractional-N frequency synthesizer of claim 17, wherein the first and second divided signals have the same frequency, and wherein the first and second divided signals differ in phase by the period of the prescribed frequency signal from the output port of the voltage-controlled oscillator, and wherein the first phase detector and the second phase detector are of the same design.

28. A method for generating frequency signals, comprising:

dividing a frequency signal output from an oscillator by a first value to produce a first divided signal;

dividing a frequency signal output from an oscillator by a second value to produce a second divided signal;

comparing the first divided signal to a reference signal to generate a first control signal;

comparing the second divided signal to said reference signal to generate a second control signal;

passing the first control signal and the second control signal through a sample-and-hold circuit, wherein the first control signal increases a charge of a capacitor of the sample-and-hold circuit and the second control signal decreases the charge of the capacitor of the sample-and-hold circuit; and

adjusting the oscillator based on an output of the sample-and-hold circuit.

29. The method of claim 28, further comprising:

selecting the first value and the second value so that the first divided signal and the second divided signal have a predetermined phase difference.

30. The method of claim 29, wherein said predetermined phase difference corresponds to one period of a voltage-controlled oscillator frequency.

31. A phase-locked-loop, comprising:

an oscillator;

a divider which divides a frequency signal output from the oscillator by a first value to produce a first divided signal and by a second value to produce a second divided signal;

a first phase detector which compares the first divided signal to a reference signal to generate a first comparison signal;

a second phase detector which compares the second divided signal to said reference signal to generate a second comparison signal; and

a sample-and-hold unit which generates a control signal for adjusting the oscillator based on the first comparison signal and the second comparison signal.

32. The phase-locked-loop of claim 31, wherein the first value and the second value generate a predetermined phase difference in the first divided signal and the second divided signal.

33. The phase-locked-loop of claim 32, wherein said predetermined phase difference corresponds to one period of the oscillator frequency.