Computer system and method of computer initialization with caching of option BIOS

• US 6,704,840 B2
• Filed: 06/19/2001
• Issued: 03/09/2004
• Est. Priority Date: 06/19/2001
• Status: Expired due to Term

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Intel Corporation
• Inventors: Siddiqi, Faraz A., Nalawadi, Rejeev K.
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US09/883,401
• Publication Number:
  US 20030023812A1
• Time in Patent Office: 994 Days
• Field of Search: 711/118, 711/165, 711/166, 711/170, 711/102, 711/103, 713/1, 713/2
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computer system and method for computer initialization with caching includes enabling at least one cache memory and then copying an option basic input/output system (BIOS) from a first memory to a Programmable Attribute Map (PAM) main memory area, the copying including executing a cache-line fill to the at least one cache memory. Initialization is then performed by providing control to the option BIOS, the execution being performed substantially from the at least one cache memory. Processor Memory Type Range Registers (MTRRs) for the PAM memory area may be programmed as write-back. The at least one cache memory may be at least one of level 1 (L1) and level 2 (L2) processor cache memories. The first memory may be a flash memory or a ROM Read Only Memory (ROM). The at least one cache memory may be flushed upon completion of the option BIOS execution.

Claims

1. A method of initialization with caching, the method comprising:

enabling at least one cache memory;

copying an option BIOS (basic input/output system) from a first memory to a PAM (Programmable Attribute Map) main memory area, the copying including executing a cache-line fill to the at least one cache memory; and

performing initialization by providing control to the option BIOS for execution, the execution being performed substantially from the at least one cache memory.

2. The method of claim 1, further comprising programming processor MTRRs (Memory Type Range Registers) for the PAM main memory area as write-back.

3. The method of claim 1, wherein enabling at least one cache memory comprises enabling at least one of level 1 (L1) and level 2 (L2) processor cache memories.

4. The method of claim 1, wherein the first memory comprises a flash memory.

5. The method of claim 1, wherein the first memory comprises a ROM (Read Only Memory).

6. The method of claim 1, further comprising flushing the at least one cache memory upon completion of the option BIOS execution.

7. A computer system comprising:

a processor;

at least one cache memory coupled to said processor;

a main memory coupled to said processor; and

a first memory having at least one option BIOS (basic input/output system) stored therein;

wherein initialization of the computer system is performed by enabling said at least one cache memory and then copying said at least one option BIOS from said first memory to a PAM (Programmable Attribute Map) area of said main memory, the copying including executing a cache-line fill to the at least one cache memory, and then performing initialization by providing control to said at least one option BIOS for execution, the execution being performed substantially from the at least one cache memory.

8. The system of claim 7, wherein initialization of the computer system includes programming processor MTRRs (Memory Type Range Registers) for said PAM main memory area as write-back.

9. The system of claim 7, wherein said at least one cache memory comprises at least one of L1 and L2 processor cache memories.

10. The system of claim 7, wherein said first memory comprises a flash memory.

11. The system of claim 7, wherein said first memory comprises a ROM (Read Only Memory).

12. The system of claim 7, wherein said at least one cache memory is flushed upon completion of said at least one option BIOS execution.

13. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method of initialization with caching, the method comprising:

enabling at least one cache memory;

copying an option BIOS (basic input/output system) from a first memory to a PAM (Programmable Attribute Map) main memory area, the copying including executing a cache-line fill to the at least one cache memory; and

performing initialization by providing control to the option BIOS for execution, the execution being performed substantially from the at least one cache.

14. The device of claim 13, further comprising programming processor MTRRs (Memory Type Range Registers) for the PAM main memory area as write-back.

15. The device of claim 13, wherein enabling at least one cache memory comprises enabling at least one of L1 and L2 processor cache memories.

16. The device of claim 13, wherein the first memory comprises a flash memory.

17. The device of claim 13, wherein the first memory comprises a ROM (Read Only Memory).

18. The device of claim 13, further comprising flushing the at least one cache memory upon completion of the option BIOS execution.