Host access to shared memory with a high priority mode
First Claim
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1. A digital system comprising:
- a memory subsystem;
a multi-channel direct memory access (DMA) subsystem with a DMA port connected to the memory subsystem for accessing the memory subsystem, each channel having priority circuitry for holding a channel priority, the DMA subsystem being operable to sequentially schedule memory accesses to the memory circuit in accordance with channel priority;
a host interface for connection to a host processor, the host interface coupled to the DMA subsystem for accessing the memory subsystem via the DMA port as a host channel, the host interface also coupled directly to the memory subsystem for accessing the memory subsystem directly;
a priority register for holding a priority of the host; and
control circuitry connected to receive the priority of the host and the priority of the DMA channels, the control circuit being operable to enable the host interface to directly access the memory subsystem when the host priority is higher than all of the DMA channel priorities, or to enable the host interface to access the memory subsystem via the DMA port when the host priority is the same as or less than the DMA channel priorities.
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Abstract
A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, the memory is connected directly to one of the requestors, such as a host processor (10), so that high bandwidth transfers can be performed. The HOM access mode is entered when a priority assigned to the host processor is set to be higher than a priority assigned to any other requester. Registers for holding the priority assignments can be written by at least one of the requesters.
119 Citations
7 Claims
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1. A digital system comprising:
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a memory subsystem;
a multi-channel direct memory access (DMA) subsystem with a DMA port connected to the memory subsystem for accessing the memory subsystem, each channel having priority circuitry for holding a channel priority, the DMA subsystem being operable to sequentially schedule memory accesses to the memory circuit in accordance with channel priority;
a host interface for connection to a host processor, the host interface coupled to the DMA subsystem for accessing the memory subsystem via the DMA port as a host channel, the host interface also coupled directly to the memory subsystem for accessing the memory subsystem directly;
a priority register for holding a priority of the host; and
control circuitry connected to receive the priority of the host and the priority of the DMA channels, the control circuit being operable to enable the host interface to directly access the memory subsystem when the host priority is higher than all of the DMA channel priorities, or to enable the host interface to access the memory subsystem via the DMA port when the host priority is the same as or less than the DMA channel priorities. - View Dependent Claims (2, 3, 4, 5, 6, 7)
an integrated keyboard (1012) connected to the microprocessor via a keyboard adapter;
a display (1014), connected to the microprocessor via a display adapter;
radio frequency (RF) circuitry (1016) connected to the microprocessor; and
an aerial (1018) connected to the RF circuitry.
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Specification
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Current AssigneeTexas Instruments, Inc.
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Original AssigneeTexas Instruments, Inc.
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InventorsSix, Laurent, Laine, Armelle, Ollivier, Gerald, Mazzocco, Daniel
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Primary Examiner(s)BATAILLE, PIERRE MICHE
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Application NumberUS09/591,535Time in Patent Office1,369 DaysField of Search711/147, 711/150, 711/151, 711/152, 711/158, 710/240, 710/244, 710/107, 710/36, 710/40, 709/216, 709/209, 709/217, 455/403, 455/426, 455/439US Class Current711/151CPC Class CodesG06F 13/18 based on priority control G...
