Method and apparatus for determining the width of a memory subsystem

• US 6,704,850 B1
• Filed: 08/23/2000
• Issued: 03/09/2004
• Est. Priority Date: 08/23/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Triscend Corp. (Advanced Micro Devices, Inc.)
• Inventors: Reynolds, Bart
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Peugh, Brian R.
• Application Number:
  US09/648,406
• Time in Patent Office: 1,294 Days
• Field of Search: 711/170, 711/171, 711/102, 711/103, 711/105, 710/305, 710/111, 710/113, 710/107
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection

Abstract

A method and apparatus for determining a width of an external memory is described. The method comprises reading a data from memory, and if the data matches an expected data key, determining the width of the memory.

Claims

1. A method of determining a width of an external memory comprising:

configuring a memory interface unit to a first memory arrangement;

determining if a memory key is found in the memory using the first memory arrangement;

if the memory key is found, identifying the first memory arrangement as the actual memory arrangement; and

otherwise, reconfiguring the memory interface unit.

2. The method of claim 1, further comprising:

determining if the actual memory arrangement leaves any extra pins that are not used for memory access; and

if there are extra pins, recovering the extra pins for other purposes.

3. The method of claim 1, further comprising:

configuring the memory interface unit using an on-chip read-only-memory.

4. The method of claim 1, further comprising:

completing system configuration using the external memory, after the correct memory arrangement is determined.

5. The method of claim 1, wherein the first memory arrangement comprises a 32 bit wide memory arrangement.

6. The method of claim 1, wherein the memory arrangements are as follows:

32 bit wide, 8 bit wide, and 16 bit wide.

7. The method of claim 1, wherein the first memory arrangement is chosen based on a most likely memory size.

8. A method of initializing a configurable system-on-chip comprising:

initializing a memory interface unit;

determining a size of an external memory;

accessing an internal read only memory (ROM);

partially configuring the configurable system-on-chip from the ROM; and

configuring the configurable system-on-chip from the external memory.

9. The method of claim 8, wherein determining a size of the external memory comprises:

determining if a memory key is found in the memory using a first memory arrangement;

if the memory key is found, identifying the first memory arrangement as the actual memory arrangement; and

otherwise, reconfiguring the memory interface unit.

10. The method of claim 9, wherein the first arrangement is determined based on a most likely memory size.

11. The method of claim 8, further comprising:

determining if an actual memory arrangement leaves any extra pins that are not used for memory access; and

if there are extra pins, reconfiguring the extra pins for other purposes.

12. The method of claim 8, wherein the memory arrangements are as follows:

32 bit wide, 8 bit wide, and 16 bit wide.

13. An apparatus for configuring a configurable system-on-chip comprising:

a programmable logic;

a memory access configuration logic comprising;

an address setting logic to configure a memory interface unit (MIU) to access an external memory;

a comparison logic to determine whether the MIU is correctly configured,

wherein the comparison logic obtains memory data from the external memory and compares the memory data to a memory key to determine whether the external memory is properly arranged;

a width determination logic to determine an accurate arrangement of the MIU based on the memory data obtained from the external memory.

14. The apparatus of claim 13, further comprising a Read Only Memory (ROM) to initialize the MIU to enable access to the external memory.

15. The apparatus of claim 13, further comprising a pin recovery logic for recovering pins not used by the MIU.

16. The apparatus of claim 13, wherein the external memory is used to complete configuration of the MIU, after the correct memory arrangement is determined.

17. A memory interface unit (MIU) to determine a size of an external memory the MIU comprising

an address setting logic to configure the MIU to access an external memory:

a comparison logic to determine whether the MIU is correctly configured;

a width determination logic to determine the accurate arrangement of the MIU; and

a pin recovery logic for reassigning pins not used by the MIU.

18. The MIU of claim 17, wherein the comparison logic obtains memory data from the memory and compares the memory data to a memory key to determine whether the memory is properly configured.

19. The MIU of claim 17, wherein the MIU is only partially configured prior to determining a size of the external memory, and the external memory is used to fully configure the MIU.

20. The MIU of claim 17, wherein the external memory is used to complete configuration of the MIU, after the correct memory arrangement is determined.

21. An apparatus for determining a width of an external memory comprising:

a means for configuring a memory interface unit to a first memory arrangement;

a determining means to determine if a memory key is found in the memory using the first memory arrangement;

if the memory key is found, an identifying means to identify the first memory arrangement as the actual memory arrangement; and

otherwise, a reconfiguring means to reconfigure the memory interface unit to a second memory arrangement.

22. The apparatus of claim 21, further comprising:

a determining means to determine if the actual memory arrangement leaves any extra pins that are not used for memory access; and

a pin recovery means to, if there are extra pins, recover the extra pins for other purposes.