Enhanced embedded logic analyzer

• US 6,704,889 B2
• Filed: 08/06/2002
• Issued: 03/09/2004
• Est. Priority Date: 10/27/1997
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rangasayee, Krishna, Herrmann, Alan L., Veenstra, Kerry
• Primary Examiner(s): BADERMAN, SCOTT T
• Application Number:
  US10/212,839
• Publication Number:
  US 20020194543A1
• Time in Patent Office: 581 Days
• Field of Search: 714/39, 714/34, 714/30, 714/725, 714/733, 714/734, 703/15, 703/16, 703/17, 703/28, 326/38, 326/39
• US Class Current: 714/39
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint. The EDA tool directs the logic analyzer to unload the data from its capture buffer for display on a computer. The breakpoint and sample number can be changed without recompiling. A JTAG port controls the logic analyzer. Inputs and outputs of the logic analyzer are routed to unbonded JTAG-enabled I/O cells. Alternatively, a user-implemented test data register provides a JTAG-like chain of logic elements through which control and output information is shifted. Stimulus cells provide control information to the logic analyzer, and sense cells retrieve data from the logic analyzer.

Claims

1. A programmable logic device (PLD) comprising:

PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD;

a logic analyzer integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer;

a JTAG (Joint Test Action Group) port arranged to receive logic analyzer commands from outside said PLD; and

a plurality of I/O cells arranged to receive command signals from said JTAG port and to provide said command signals to said logic analyzer.

2. A PLD as recited in claim 1 wherein said I/O cells are arranged to drive said command signals into the core of said PLD while said PLD is in a normal operating environment.

3. A programmable logic device (PLD) comprising:

PLD circuitry representing one iteration of an electronic design in a design process to create a final PLD;

a logic analyzer integrated within said PLD circuitry such that a portion of said PLD circuitry is connected to said logic analyzer;

a JTAG (Joint Test Action Group) port arranged to receive logic analyzer commands from outside said PLD; and

a test data register arranged to provide serial data from said JTAG port to said logic analyzer, whereby said logic analyzer receives said commands from outside said PLD via said JTAG port.

4. A PLD as recited in claim 3 wherein said test data register includes:

a plurality of stimulus cells for providing said serial data to said logic analyzer; and

a plurality of sense cells for receiving said captured data from said logic analyzer.

5. A method for debugging a programmable logic device (PLD), said method comprising:

compiling an electronic design and inserting a logic analyzer to produce a design file;

programming said PLD with said design file, said logic analyzer being embedded in said PLD;

connecting a JTAG (Joint Test Action Group) port of said PLD to said logic analyzer to control said logic analyzer; and

receiving captured data from said embedded logic analyzer via said JTAG port, whereby said PLD may be debugged.

6. A method as recited in claim 5 further comprising:

providing serial data from said JTAG port to first I/O cells of said PLD, said first I/O cells being arranged to load said serial data into said logic analyzer; and

receiving said captured data from said logic analyzer into second I/O cells, said second I/O cells being arranged to provide said captured data to said JTAG port.

7. A method as recited in claim 5 further comprising:

forming a test data register in the core of said PLD through which signals between said JTAG port and said logic analyzer may pass serially.

8. A method for debugging a programmable logic device (PLD), said method comprising:

compiling an electronic design and inserting a logic analyzer to produce a design file;

programming said PLD with said design file, said logic analyzer being embedded in said PLD;

delivering logic analyzer commands through a JTAG port of said PLD to said logic analyzer; and

receiving captured data from said logic analyzer via said JTAG port of said PLD, whereby said PLD may be debugged.

9. A method as recited in claim 8 wherein said commands and said captured data pass serially through said JTAG port, wherein said commands are delivered in parallel to said logic analyzer, and wherein said captured data is captured in parallel from said logic analyzer.

10. A computer-readable medium comprising computer code for debugging a programmable logic device (PLD), said computer code effecting the following:

compiling an electronic design and inserting a logic analyzer to produce a design file;

programming said PLD with said design file, said logic analyzer being embedded in said PLD;

connecting a JTAG (Joint Test Action Group) port of said PLD to said logic analyzer to control said logic analyzer; and

receiving captured data from said embedded logic analyzer via said JTAG port, whereby said PLD may be debugged.

11. A computer-readable medium as recited in claim 10 further comprising computer code for effecting:

providing serial data from said JTAG port to first I/O cells of said PLD, said first I/O cells being arranged to load said serial data into said logic analyzer; and

receiving said captured data from said logic analyzer into second I/O cells, said second I/O cells being arranged to provide said captured data to said JTAG port.

12. A computer-readable medium as recited in claim 10 further comprising computer code for effecting:

forming a test data register in the core of said PLD through which signals between said JTAG port and said logic analyzer may pass serially.

13. A computer-readable medium comprising computer code for debugging a programmable logic device (PLD), said computer code effecting the following:

compiling an electronic design and inserting a logic analyzer to produce a design file;

programming said PLD with said design file, said logic analyzer being embedded in said PLD;

delivering logic analyzer commands through a JTAG port of said PLD to said logic analyzer; and

receiving captured data from said logic analyzer via said JTAG port of said PLD, whereby said PLD may be debugged.

14. A computer-readable medium as recited in claim 13 wherein said commands and said captured data pass serially through said JTAG port, wherein said commands are delivered in parallel to said logic analyzer, and wherein said captured data is captured in parallel from said logic analyzer.

15. A system for programming a programmable logic device (PLD), said system comprising:

a computer;

an electronic design including PLD circuitry present in said computer;

a logic analyzer integrated within said electronic design such that a portion of said PLD circuitry is connected to said logic analyzer;

a JTAG (Joint Test Action Group) port integrated within said electronic design and arranged to receive logic analyzer commands;

means for performing the function of controlling said logic analyzer using said JTAG port, said means integrated within said electronic design and arranged to receive command signals from said JTAG port and to provide said command signals to said logic analyzer;

a programmable logic device (PLD); and

an interface between said computer and said PLD, whereby said computer is used to program said PLD.

16. A system as recited in claim 15 wherein said means includes:

unbonded I/O cells through which signals pass between said JTAG port and said logic analyzer.

17. A system as recited in claim 15 wherein said means includes:

a test data register implemented in the core of said PLD through which signals pass between said JTAG port and said logic analyzer.

18. A system as recited in claim 15 further comprising:

a plurality of logic analyzers integrated within said electronic design; and

means for performing the function of selecting one of said logic analyzers, wherein said means for controlling controls said selected logic analyzer, whereby said selected logic analyzer receives said commands from outside said PLD and operates appropriately.