Method for testing integrated circuits with an automatic test equipment

• US 6,704,893 B1
• Filed: 08/15/2000
• Issued: 03/09/2004
• Est. Priority Date: 09/14/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics NV
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Chichkov, Anton, Bauwens, Peter
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US09/638,904
• Time in Patent Office: 1,302 Days
• Field of Search: 714/724, 714/744
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence

Abstract

An automatic test equipment is used to test integrated circuits. The test comprises applying signals to each input pin of the circuit at predetermined timings and in detecting output signals at the output pins of the circuit at predetermined timings. Each succession of timings, or time-plates, for an input pin and the corresponding output pin is controlled by a timing generator in the test equipment. When the number n of time-plates is greater than the number m of timing generators, the test is realized in several steps. The timing generators, which are reused for other time-plates during a second or further step, are selected in a way that minimizes testing time. The timing generators which are reused are those which require a minimum number of programming changes from the time-plate implemented during the first step.

Claims

1. A method for testing integrated circuits by the use of an automatic test equipment, the testing comprising applying to each input pin signals at determined timings and in detecting the output signals at the output pins at predetermined timings, wherein each succession of timings, or time-plates, for an input pin and the corresponding output pin is controlled by a timing generator in the automatic test equipment and wherein, when the number n of time-plates is superior to the number m of timing generators, the test is realized in several steps, timing generators being reused for implementing other time-plates during a second or further step, wherein, in order to minimize the testing time, the timing generators which are reused during the second step are timing generators which impose a minimum number of programming changes from the time-plate implemented during the first step to the time-plate implemented for the second step.

2. A method according to claim 1, wherein the number of changes to be counted for the selection of the timing generators to be reprogrammed is the addition of timing changes and of format changes.

3. A method according to claim 1, wherein the time-plates which will be used during successive steps remain implemented on the same timing generator.

4. A method according to claim 1, wherein, in order to select the timing generators which will be reused during the further step(s), for every possible couple of time-plates, the number of changes to be implemented in order to convert one time-plate to the other is determined, and the timing generators which will be reused from one step to the next step and the time-plates which will be implemented in these timing generators are those for which the number of changes is minimum in order to convert the time-plate used during the said one step to the time-plate used during the next step.

5. A method according to claim 4, wherein said number for all couples are kept in a memory in order to be used sequentially.

6. An automatic test equipment for testing integrated circuits comprising means for applying to each input pin of the integrated circuit, signals at determined timings, means for detecting the output signals at the output pins at predetermined timings, timing generators, each of these timings generators having the function to control the succession of timings, or time-plates, for an input pin and the corresponding output pin, and means for realizing the test in several steps when the number n of time-plates is superior to the number m of timing generators, said means for realizing the test in several steps comprising means for reusing timing generators for implementing other time-plates during a second or further step, wherein the means for reusing the timing generators comprise, in order to minimize the testing time, means for determining the timing generators which impose a minimum number of programming changes from the time-plate implemented during the first step to the time-plate implemented for the second step.

7. An automatic test equipment according to claim 6, wherein the means for determining the timing generators which impose a minimum of programming changes, comprise means for adding the number of timing changes to the number of format changes.

8. An automatic test equipment according to claim 6, wherein the means for determining the timing generators which impose a minimum number of programming changes, comprise means for using the same timing generator for time-plates used during successive steps.

9. A method for manufacturing an integrated circuit comprising a testing step making use of an automatic test equipment, the testing consisting in applying to each input pin signals at determined timings and in detecting the output signals at the output pins at predetermined timings, wherein each succession of timings, or time-plates, for an input pin and the corresponding output pin is controlled by a timing generator in the automatic test equipment and wherein, when the number n of time-plates is superior to the number m of timing generators, the test is realized in several steps, timing generators being reused for implementing other time-plates during a second or further step, wherein, in order to minimize the testing time, the timing generators which are reused during the second step are timing generators which impose a minimum number of programming changes from the time-plate implemented for the first step to the, time-plate implemented for the second step.