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Process for fast cell placement in integrated circuit design

  • US 6,704,915 B1
  • Filed: 06/12/2001
  • Issued: 03/09/2004
  • Est. Priority Date: 01/08/2001
  • Status: Expired due to Fees
First Claim
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1. A process for altering a distribution of N cells in a first integrated circuit chip layout to position the cells in a second integrated circuit chip layout, the first and second layouts each having respective bounds, the process comprising steps of:

  • a) establishing an x,y grid for the first and second integrated chip layouts such that each cell has x,y coordinates in the first layout and a height in the y-direction;

    b) establishing K columns based on the bounds of the second layout in the x-direction, K being an integer;

    c) sorting the cells to the K columns in order of cell x-coordinates in the first layout to establish x-coordinates in the second layout for each cell based on the x-coordinates of the respective column, each column having a height in the y-direction; and

    d) sorting the cells in each column to establish y-coordinates in the second layout for each cell based on the height of the cells in the column and the height of the column.

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