Optical reflective structures and method for making

• US 6,706,546 B2
• Filed: 01/08/2001
• Issued: 03/16/2004
• Est. Priority Date: 10/09/1998
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Peters, Michael, Kuwabara, Kiyoshi, Wang, Wen-Chou Vincent, Takahashi, Yashuhito, Yoshimura, Tetsuzo, Beilin, Solomon I., Inao, Masaaki
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US09/757,052
• Publication Number:
  US 20020039464A1
• Time in Patent Office: 1,163 Days
• Field of Search: 438/22, 438/24, 438/31, 438/106, 438/107, 438/108, 438/128, 438/129, 438/464, 438/462, 385/15, 385/123, 385/129, 385/130, 385/131, 385/142, 385/144, 653/85, 653/86, 216/24
• US Class Current: 438/31
• CPC Class Codes: G02B 2006/12104 Mirror; Reflectors or the like
• CPC Class Codes: G02B 2006/12107 Grating
• CPC Class Codes: G02B 2006/12173 Masking
• CPC Class Codes: G02B 6/06 the relative position of the fibres being the same at both ends, e.g. for transporting images
• CPC Class Codes: G02B 6/10 of the optical waveguide type G02B6/02, G02B6/24 take precedence; devices or arrangements for the control of light by electric, magnetic, electro-magnetic or acoustic means G02F1/00; transferring the modulation of modulated light G02F2/00; optical logic elements G02F3/00; optical analogue/digital converters G02F7/00
• CPC Class Codes: G02B 6/12002 Three-dimensional structures
• CPC Class Codes: G02B 6/124 Geodesic lenses or integrated gratings
• CPC Class Codes: G02B 6/13 Integrated optical circuits characterised by the manufacturing method
• CPC Class Codes: G02B 6/132 by deposition of thin films
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: G02B 6/26 Optical coupling means G02B6/36, G02B6/42 take precedence
• CPC Class Codes: G02B 6/42 Coupling light guides with opto-electronic elements
• CPC Class Codes: G02B 6/4214 the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device G02B6/4246 takes precedence
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/05568 : the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 : Single external layer
• CPC Class Codes: H01L 2224/05611 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/0101 : Neon [Ne]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/0274 : Optical details, e.g. printed circuits comprising integral optical means H05K1/0269 takes precedence; coupling light guides with opto-electronic components G02B6/42
• CPC Class Codes: H05K 1/14 : Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00

Abstract

A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.

Claims

1. A method of constructing an electronic circuit assembly comprising the steps of:

a) forming at least one electrode on a substrate;

b) forming a layer of undercladding material upon the substrate and over the electrode;

c) forming a wave guide core layer on said layer of cladding material;

d) patterning said wave guide layer to produce at least one optical wave guide and exposed undercladding material;

e) forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide;

f) forming at least one via aperture through said overcladding material and said undercladding material; and

g) disposing a conductive material in said via aperture to produce an electronic circuit assembly.

2. The method of claim 1 wherein said disposing step (g) additionally comprises disposing a partial layer of the conductive material over the overcladding material.

3. The method of claim 1 additionally comprising forming a patterned resist on the overcladding material prior to said disposing step (g).

4. The method of claim 2 additionally comprising forming a patterned resist on the overcladding material prior to said disposing step (g).

5. The method of claim 1 wherein said via aperture terminates in said electrode.

6. The method of claim 4 additionally comprising forming a patterned resist on the overcladding material prior to said disposing step (g).

7. The method of claim 1 wherein said forming step (f) additionally comprises removing a portion of the optical wave guide.

8. The method of claim 6 wherein said forming step (f) additionally comprises removing a portion of the optical wave guide.

9. The method of claim 1 wherein said forming step (f) additionally comprises forming a forty-five degree sidewall in said optical wave guide.

10. The method of claim 8 wherein said forming step (f) additionally comprises forming a forty-five degree sidewall in said optical wave guide.

11. The method of claim 9 wherein said disposing step (g) additionally comprises forming a forty-five degree optical reflective surface on said forty-five degree sidewall.

12. The method of claim 10 wherein said disposing step (g) additionally comprises forming a forty-five degree optical reflective surface on said forty-five degree sidewall.

13. The method of claim 1 wherein said forming step (f) additionally comprises forming the via aperture to have opposed via walls such that a portion of said optical wave guide is generally centrically disposed in the via aperture between the via walls.

14. The method of claim 13 wherein said disposing step (g) additionally comprises disposing conductive material on said opposed via walls and against said portion of said optical wave guide.

15. A method of constructing an electronic circuit assembly comprising the steps of:

a) forming at least one electrode on a substrate;

b) disposing an electro-optic device on the substrate;

c) forming a layer of undercladding material upon the substrate and over the electrode and the electro-optic device;

d) disposing a second electrode on the layer of undercladding material;

e) disposing an intermediate layer of cladding material over exposed portions of the layer of undercladding material and over the second electrode;

f) forming a wave guide core layer on said layer of cladding material;

g) patterning said wave guide layer to produce at least one optical wave guide and exposed undercladding material;

h) forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide;

i) forming at least one via aperture through said overcladding material and said undercladding material; and

j) disposing a conductive material in said via aperture to produce an electronic circuit assembly.

16. The method of claim 15 additionally comprising polishing the layer of the cladding material prior to the disposing step (d) until a top of the electrode is aligned with the cladding material.

17. The method of claim 15 additionally comprising forming, prior to said disposing step (d), an opening in said layer of undercladding material to expose a portion of the electro-optic device;

and disposing conductive material in said opening and in contact with said electro-optic device.

18. The method of claim 16 additionally comprising forming, prior to said disposing step (d), an opening in said layer of undercladding material to expose a portion of the electro-optic device;

and disposing conductive material in said opening and in contact with said electro-optic device.

19. The method of claim 15 wherein said disposing step (j) additionally comprises disposing a partial layer of the conductive material over the overcladding material.

20. The method of claim 15 additionally comprising forming a patterned resist on the overcladding material prior to said disposing step (j).

21. The method of claim 18 additionally comprising forming a patterned resist on the overcladding material prior to said disposing step (j).

22. The method of claim 15 wherein said via aperture terminates in said electrode.

23. The method of claim 21 additionally comprising forming a patterned resist on the overcladding material prior to said disposing step (j).

24. The method of claim 15 wherein said forming step (i) additionally comprises removing a portion of the optical wave guide.

25. The method of claim 23 wherein said forming step (i) additionally comprises removing a portion of the optical wave guide.

26. The method of claim 15 wherein said forming step (i) additionally comprises forming a forty-five degree sidewall in said optical wave guide.

27. The method of claim 25 wherein said forming step (i) additionally comprises forming a forty-five degree sidewall in said optical wave guide.

28. The method of claim 26 wherein said disposing step (j) additionally comprises forming a forty-five degree optical reflective surface on said forty-five degree sidewall.

29. The method of claim 27 wherein said disposing step (j) additionally comprises forming a forty-five degree optical reflective surface on said forty-five degree sidewall.

30. The method of claim 15 wherein said forming step (i) additionally comprises forming the via aperture to have opposed via walls such that a portion of said optical wave guide is generally centrically disposed in the via aperture between the via walls.

31. The method of claim 30 wherein said disposing step (j) additionally comprises disposing conductive material on said opposed via walls and against said portion of said optical wave guide.

32. A method of constructing an electronic circuit assembly comprising the steps of:

a) forming a layer of undercladding material upon a first substrate;

b) forming a wave guide core layer on said layer of cladding material;

c) patterning said wave guide layer to produce at least one optical wave guide and exposed undercladding material;

d) forming a layer of overcladding material upon the exposed undercladding material;

e) forming at least one via aperture through said overcladding material and said undercladding material;

f) disposing a conductive material in said via aperture leaving a first portion of the conductive material exposed; and

g) coupling the first portion of the conductive material to a second substrate to produce an electronic circuit.

33. The method of claim 32 additionally comprising removing the first substrate to expose a second portion of the conductive material.

34. The method of claim 33 additionally comprising disposing at least one electrode on the exposed second portion of the conductive material.

35. The method of claim 34 additionally comprising coupling the disposed electrode to another electronic circuit assembly.

36. The method of claim 33 additionally comprising removing the second substrate to expose the first portion of the conductive material.

37. The method of claim 35 additionally comprising removing the second substrate to expose the first portion of the conductive material.

38. A method of constructing an electronic circuit assembly comprising the steps of:

a) forming a layer of undercladding material upon a first substrate;

b) forming a wave guide core layer on said layer of cladding material;

c) patterning said wave guide layer to produce at least one optical wave guide and exposed undercladding material;

d) forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide;

e) disposing an electrode on the layer of overcladding material;

f) disposing an electro-optic device on the layer of overcladding material;

g) depositing an intermediate layer of cladding material over exposed overcladding material and over the electrode and the electro-optic device;

h) removing a portion of the intermediate layer of cladding material and a portion of a top of the electrode until a plane along the top of the electro-optic device registers with a residual electrode surface and a residual cladding surface respectively remaining after removal of the portion of the top of the electrode and the portion of the intermediate layer of cladding material;

i) disposing a second electrode on the residual electrode surface;

j) coupling the second electrode to a second substrate;

k) removing the first substrate to expose the undercladding material;

l) forming at least one via aperture through said overcladding material and said undercladding material; and

m) disposing a conductive material in said via aperture to produce an electronic circuit assembly.