Method for forming multiple structures in a semiconductor device

• US 6,706,571 B1
• Filed: 10/22/2002
• Issued: 03/16/2004
• Est. Priority Date: 10/22/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: An, Judy Xilin, Tabery, Cyrus E., Yu, Bin, Wang, Haihong
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Kennedy, Jennifer M.
• Application Number:
  US10/274,951
• Time in Patent Office: 511 Days
• Field of Search: 438/283, 438/286, 438/157, 438/585
• US Class Current: 438/157
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures.

Claims

1. A method of forming a plurality of fins in a FinFET device, comprising:

depositing a dielectric layer over a silicon on insulator (SOI) wafer, the SOI wafer comprising a conductive layer on an insulating layer;

forming a resist mask over portions of the dielectric layer;

etching a trench in a portion of the dielectric layer not covered by the resist mask, the trench having two side walls;

forming spacers adjacent the two sidewalls of the trench, the spacers comprising a conductive material and having a width ranging from about 100 Å

to about 500 Å

;

etching the dielectric layer to form dielectric structures located below the spacers, the dielectric structures having a width approximately equal to the width of the spacers;

etching the conductive layer to form the plurality of fins; and

removing the spacers and the dielectric structures.

2. The method of claim 1, wherein a pitch of the plurality of fins ranges from about 500 Å

to about 1500 Å

.

3. The method of claim 1, wherein the forming a resist mask over a portion of the dielectric layer includes:

depositing a photoresist material over the dielectric layer, and

forming at least a first opening in the photoresist material, wherein the opening exposes the dielectric layer and a distance between at least two of the plurality of fins is defined in part by the width of the first opening.

4. The method of claim 1, wherein the etching a trench comprises:

etching about 300 Å

to about 1000 Å

of the dielectric layer not covered by the resist mask.

5. The method of claim 1, wherein the insulating layer comprises a buried oxide layer and the conductive layer comprises at least one of silicon and germanium.

6. The method of claim 5, wherein the spacers comprise silicon.

7. The method of claim 1, wherein the dielectric layer comprises a silicon oxide.

8. The method of claim 1, wherein the plurality of fins consists of two fins.

9. A method of manufacturing a semiconductor device, comprising:

depositing a film over a conductive layer, the conductive layer being used to form a plurality of fin structures;

etching at least one trench in a portion of the film, a first one of the at least one trench having two side walls;

forming spacers adjacent the two sidewalls of the first trench, the spacers having a first width and comprising a conductive material;

etching the film, the etching terminating on the conductive layer with the spacers acting as a mask to prevent etching of portions of the film located below the spacers, the un-etched portions of the film forming a first plurality of structures approximately equal in width to the first width;

etching the conductive layer, the first plurality of structures acting as a mask to prevent portions of the conductive layer from being etched, the un-etched portions of the conductive layer forming the fin structures;

forming a source region and a drain region;

depositing a gate material over the fin structures; and

patterning and etching the gate material to form at least one gate electrode.

10. The method of claim 9, wherein a distance between the plurality of fin structures ranges from about 500 Å

to about 1500 Å

.

11. The method of claim 9, wherein the etching at least one trench comprises:

etching about 300 Å

to about 1000 Å

into a top surface of the film not covered by a resist mask.

12. The method of claim 9, wherein the etching at least one trench comprises:

etching at least one trench having a predetermined width, wherein a pitch of at least two of the plurality of fin structures is based on the predetermined width.

13. The method of claim 9, wherein the conductive layer is formed on a buried oxide layer that is formed on a semiconducting material, the conductive layer comprising at least one of silicon and germanium, the film comprising a silicon oxide and the spacers comprising silicon.

14. The method of claim 9, wherein the at least one gate electrode comprises two gate electrodes, a first gate electrode being located on a first side of the plurality of fin structures and a second gate electrode being located on an opposite side of the plurality of fin structures.

15. A method of forming a plurality of structures in a semiconductor device, comprising:

depositing a film over a conductive layer;

etching at least one trench in a portion of the film;

forming conductive spacers along sidewalls of the at least one trench;

etching the film, the etching terminating on the conductive layer; and

etching the conductive layer to form the plurality of structures wherein the semiconductor device comprises a finFET device and the plurality of structures comprise fins.

16. The method of claim 15, wherein the film comprises a dielectric material and the etching the film forms dielectric structures below the spacers, the method further comprising:

removing the spacers and the dielectric structures.

17. The method of claim 15, wherein the plurality of structures comprises a plurality of fins and the at least one trench comprises two trenches, the two trenches being laterally separated by a predetermined distance and each of the two trenches having a predetermined width.

18. The method of claim 17, wherein a distance between a first fin and a second fin is defined by the predetermined width.

19. The method of claim 18, wherein a distance between the second fin and a third fin is defined by the predetermined distance.