Buried zener diode structure and method of manufacture

• US 6,706,606 B2
• Filed: 06/19/2003
• Issued: 03/16/2004
• Est. Priority Date: 06/27/2002
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Oglesby, Darrel C. Jr., Romas, Gregory G. Jr.
• Primary Examiner(s): Nguyen, Vanthu
• Assistant Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US10/465,748
• Publication Number:
  US 20040000700A1
• Time in Patent Office: 271 Days
• Field of Search: 257/551, 257/606, 438/380, 438/328, 438/545, 438/548
• US Class Current: 438/328
• CPC Class Codes: H01L 29/66106 Zener diodes
• CPC Class Codes: H01L 29/866 Zener diodes

Abstract

A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.

Claims

1. A method of manufacturing a buried Zener diode, the method comprising the steps of:

providing a P-type semiconductor substrate having an upper surface;

depositing an N-type buried layer onto the upper surface of the P-type substrate and driving the N-type buried layer into the P-type substrate to form an NPN buried collector (DUF) having an exposed upper surface, and that defines an exposed upper surface associated with the P-type substrate;

placing a P-type implant/deposition (PBL) within the DUF such that the PBL has an exposed upper surface, the PBL defining a diode tank, and further defining the exposed upper surface associated with the DUF;

encasing the exposed upper surface of the P-type substrate, the exposed upper surface of the DUF, and the exposed upper surface of the PBL with an epitaxial (EPI) layer having an upper surface;

encasing the upper surface of the EPI layer with a field oxide;

creating two voids between the upper surface of the EPI layer and the diode tank defined by the PBL;

placing a P+ deposition (ISO) within each void, and driving the P+ deposition into the diode tank such that the ISO merges with the PBL;

placing an NPN base implant/deposition within each void, and driving the NPN base implant/deposition into the ISO to form a NPN transistor base, the NPN base implant/deposition having an exposed upper surface and a doping concentration significantly higher than that of the ISO;

placing an N++ emitter diffusion encompassing a predetermined NPN base implant/deposition such that the emitter diffusion extends laterally beyond the NPN transistor base and its associated underlying isolation, the emitter diffusion having an exposed upper surface within the associated void; and

applying a contact etch to expose the upper surface of the NPN base implant/deposition and to expose the upper surface of the emitter diffusion, wherein the N++ emitter diffusion and the predetermined NPN base implant/deposition define a N++/P+ Zener diode junction that is removed from the exposed upper surface of the N++ emitter diffusion.

2. The method of manufacturing a buried Zener diode according to claim 1 further comprising:

providing an electrical interconnection to the upper surface of the emitter diffusion defining a cathode; and

providing an electrical interconnection to the upper surface of the NPN base implant/deposition devoid of emitter diffusion defining an anode.