Method for tiling unit cells

• US 6,706,619 B2
• Filed: 03/16/2002
• Issued: 03/16/2004
• Est. Priority Date: 03/16/2002
• Status: Expired due to Term

• Current Assignee: NeoPhotonics Corporation (Lumentum Holdings Inc.)
• Original Assignee: MEMX, Inc. (Lumentum Holdings Inc.)
• Inventors: Miller, Samuel Lee, Rodgers, Murray Steven
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, G.
• Application Number:
  US10/099,140
• Publication Number:
  US 20030176046A1
• Time in Patent Office: 731 Days
• Field of Search: 438/460-62, 438/50-53, 438/414-17, 257/254, 216/2, 216/52, 216/82, 385/14-18, 338/2
• US Class Current: 438/460
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81B 7/04 Networks or arrays of similar microstructural devices
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

A method for creating a layout of at least a portion of a microelectromechanical system is disclosed. In one embodiment, a plurality of die are formed on a wafer. Each die includes a plurality of rows of a plurality of mirror assemblies, a plurality of off-chip electrical contacts, and an electrical trace bus that is disposed between adjacent pairs of rows. This electrical trace bus is electrically interconnected with mirror assemblies in at least one of the rows. A plurality of these die are formed on a wafer. A chip is separated from the wafer such that a chip width is an integer multiple of the die width and such that a chip height is an integer number of the rows of mirror assemblies without requiring the chip height to be an integer multiple of the die height.

Claims

1. A method for making a chip, comprising the steps of:

defining a first configuration for a die that corresponds with an area encompassed by a single exposure field of a photolithographic stepper, wherein said defining step comprises providing a plurality of rows of a plurality of mirror assemblies, a plurality of off-chip electrical contacts for each of said plurality of rows, and an electrical trace bus located between at least some adjacent pairs of rows of said plurality of rows and that is electrically interconnected with at least some of said mirror assemblies of at least one said row of the two said rows between which said electrical trace bus is located, wherein said die comprises a first die dimension that is a distance between first and second sides of said die, as well as a second die dimension that is a distance between third and fourth sides of said die, wherein said first die dimension and said second die dimension are orthogonal to each other, wherein said plurality of rows of said plurality of mirror assemblies extend in said first die dimension, and wherein said plurality of rows of said plurality of mirror assemblies are spaced in said second die dimension;

forming a plurality of the same said die on a wafer; and

dicing said wafer into a chip, wherein said dicing step comprises the steps of;

providing a first chip dimension for said chip that is an integer multiple of said first die dimension; and

providing a second chip dimension for said chip that is an integer multiple of one of said plurality of rows of said plurality of mirror assemblies without requiring said second chip dimension to be an integer multiple of said second die dimension, wherein said first and second chip dimensions are orthogonal.

2. A method, as claimed in claim 1, wherein:

said defining a first configuration step comprises providing each of said plurality of mirror assemblies with a mirror and at least one actuator.

3. A method, as claimed in claim 1, wherein:

said defining a first configuration step comprises disposing each of said plurality of rows in at least substantially parallel relation.

4. A method, as claimed in claim 1, wherein:

said defining a first configuration step comprises disposing a portion of said plurality of off-chip electrical contacts at least generally at each end of each of said plurality of rows.

5. A method, as claimed in claim 1, wherein:

each of said plurality of mirror assemblies comprises a mirror, wherein each said mirror comprises a center, wherein said defining a first configuration step comprises disposing said center of each said mirror in each of said plurality of rows at least generally along a common reference line.

6. A method, as claimed in claim 1, wherein:

each of said plurality of mirror assemblies comprises a mirror, wherein each said mirror comprises a center, wherein said defining a first configuration step comprises disposing said center of each said mirror in each of said plurality of rows other than along a common reference line.

7. A method, as claimed in claim 1, wherein:

said defining a first configuration step comprises electrically interconnecting each said electrical trace bus with only one row of said adjacent pair of said plurality of rows.

8. A method, as claimed in claim 1, wherein:

said defining a first configuration step comprises electrically interconnecting each said electrical trace bus with both rows of said adjacent pair of said plurality of rows.

9. A method, as claimed in claim 1, wherein:

said defining a first configuration step comprises allowing each said mirror assembly to be electrically accessed from a perimeter region of said chip after said dicing step.

10. A method, as claimed in claim 1, wherein:

each said mirror assembly comprises a mirror that in turn comprises a mirror center, wherein said defining a first configuration step comprises spacing apart said mirror centers of each adjacent pair of said mirrors in each of said plurality of rows by a first distance, wherein said dicing step comprises defining said first chip dimension further as an integer multiple of said first distance.

11. A method, as claimed in claim 1, wherein:

said forming a plurality of said die step comprises disposing said plurality of die in a plurality of die rows and a plurality of die columns on said wafer.

12. A method, as claimed in claim 11, further comprising the step of:

electrically interconnecting each adjacent pair of said die in each of said plurality of die rows.

13. A method, as claimed in claim 12, further comprising a step of:

electrically interconnecting adjacent pairs of said die that are only in the same said die row.

14. A method, as claimed in claim 11, wherein:

each said die has a die width and a die height, wherein said die width is measured in a direction in which its corresponding said die row extends, and wherein said die height is measured in a direction in which its corresponding said die column extends.

15. A method, as claimed in claim 14, wherein:

said providing a first dimension step of said dicing step comprises using a complete said die width of each said die in each said die row.

16. A method, as claimed in claim 14, wherein:

said providing a second dimension step of said dicing step comprises using a complete said die height of each said die in each said die row.

17. A method, as claimed in claim 14, wherein:

said providing a second dimension step of said dicing step comprises using only a portion of said die height of each said die in at least one of said die rows.

18. A method, as claimed in claim 14, wherein:

said providing a second dimension step of said dicing step comprises using only a portion of said die height of each said die in at least one of said die rows and using a complete said die height of each said die in at least one of said die rows.

19. A method, as claimed in claim 1, wherein:

said dicing step comprises defining a square configuration for said chip.

20. A method, as claimed in claim 1, wherein:

said dicing step comprises defining a rectangular configuration for said chip.

21. A method, as claimed in claim 1, wherein:

said dicing step comprises sawing said wafer.

22. A method for creating a layout for a microelectromechanical system to be fabricated from a reticle set that is based upon said layout, said method comprising the steps of:

drawing a first unit cell precursor, wherein said drawing step comprises drawing a plurality of electrical traces;

making a first unit cell precursor copy of said first unit cell precursor;

performing a first positioning step comprising positioning part of said first unit cell precursor copy in interfacing relation with part of said first unit cell precursor, wherein said first unit cell precursor copy and said first unit cell precursor collectively define a first unit cell; and

making a first unit cell copy of said first unit cell; and

performing a second positioning step comprising positioning part of said first unit cell copy in interfacing relation with part of said first unit cell, wherein said drawing step comprises routing said plurality of electrical traces within said first unit cell precursor such that corresponding pairs of said electrical traces on interfacing portions of said first unit cell precursor copy and said first unit cell precursor, and on interfacing portions of said second unit cell copy and said second unit cell, are aligned and disposed in interfacing relation.

23. A method, as claimed in claim 22, wherein:

wherein said drawing step comprises defining at least a portion of a boundary of said first unit cell precursor by where at least some ends of said plurality of electrical traces terminate.

24. A method, as claimed in claim 22, wherein:

said drawing step comprises defining first and second sides that are collectively defined by where at least some ends of at least some of said plurality of electrical traces terminate.

25. A method, as claimed in claim 24, wherein:

said drawing step comprises having at least some said ends of at least some of said plurality of electrical traces terminate at other than said first and second sides.

26. A method, as claimed in claim 24, wherein:

said drawing step comprises drawing at least some of said plurality of electrical traces with one said end terminating at said first side and an opposite said end terminating at said second side.

27. A method, as claimed in claim 24, wherein:

said drawing step comprises drawing at least some of said plurality of electrical traces with one said end terminating at either said first or second side and with an opposite said end terminating at other than said first and second sides.

29. A method, as claimed in claim 22, wherein:

said performing a first positioning step comprises disposing said first unit cell precursor copy in a first direction from said first unit cell precursor, wherein said drawing step comprises disposing opposite ends of each said electrical trace that terminate at said first and second sides in offset relation in a direction that is orthogonal to said first direction.

30. A method, as claimed in claim 22, wherein:

said drawing step comprises drawing at least one microstructure assembly and interconnecting said at least one said microstructure assembly with at least one of said plurality of electrical traces.

31. A method, as claimed in claim 30, wherein:

said drawing step comprises drawing an odd number of said microstructure assemblies and interconnecting each said microstructure assembly with at least one of said plurality of electrical traces.

32. A method, as claimed in claim 22, wherein:

said drawing step comprises drawing at least one mirror assembly and interconnecting said at least one mirror assembly with at least one of said plurality of electrical traces.

33. A method, as claimed in claim 22, wherein:

said drawing step consisting essentially of drawing said plurality of electrical traces.

34. A method, as claimed in claim 22, wherein:

said performing a first positioning step comprises disposing said first unit cell precursor and said first unit cell precursor copy in different orientations.

35. A method, as claimed in claim 22, wherein:

said performing a first positioning step comprises disposing both said first unit cell precursor and said first unit cell precursor copy in a first orientation, and thereafter rotating said first unit cell precursor copy about at least one axis.

36. A method, as claimed in claim 22, wherein:

said performing a first positioning step comprises disposing both said first unit cell precursor and said first unit cell precursor copy in a first orientation, and thereafter rotating said first unit cell precursor copy about at least a first axis and thereafter about a second axis that is different from said first axis.

37. A method, as claimed in claim 22, wherein:

said performing a second positioning step comprises translating said first unit cell copy in a first direction from a location of said first cell.

38. A method, as claimed in claim 22, further comprising the step of:

performing a third positioning step comprising positioning part of a second said first unit cell copy in interfacing relation with part of said first unit cell copy.

39. A method, as claimed in claim 22, further comprising the step of:

performing a third positioning step comprising positioning part of a plurality of said first unit cell copies in end-to-end relation, wherein each of said plurality of said first unit cell copies is in interfacing relation with another said first unit cell copies.

28. A method, as claimed in claimed 24, wherein:

said drawing step comprises disposing a first number of said ends at said first side and disposing a second number of said ends at said second side, wherein said first and second numbers are different.