Chip interconnect bus

• US 6,707,077 B2
• Filed: 03/16/2002
• Issued: 03/16/2004
• Est. Priority Date: 03/16/2002
• Status: Expired due to Term

• Current Assignee: NeoPhotonics Corporation (Lumentum Holdings Inc.)
• Original Assignee: MEMX, Inc. (Lumentum Holdings Inc.)
• Inventors: Miller, Samuel Lee
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US10/100,173
• Publication Number:
  US 20030173596A1
• Time in Patent Office: 731 Days
• Field of Search: 257/203, 257/207, 257/210, 257/211, 257/620, 385/18, 385/128, 385/17, 385/20, 385/16-23, 385/14, 359/291, 359/265, 359/872, 359/223, 359/881, 359/871, 359/877, 438/692, 361/220, 361/222, 361/233, 361/234
• US Class Current: 257/203
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means
• CPC Class Codes: H10B 99/10 Memory cells having a cross-point geometry

Abstract

An interconnect bus for a microelectromechanical system is disclosed. Various attributes for an electrical trace bus that facilitate the routing of signals throughout at least a portion of the system and/or the layout of the microelectromechanical system on a wafer are disclosed.

Claims

1. A chip, comprising:

a first row of a plurality of chip sections, wherein a width dimension of each said chip section is equal to one die width, and wherein said plurality of chip sections are disposed such that said width dimension of each of said plurality of chip sections defines a length dimension of said first row;

second and third rows of a plurality of electrical load-based microstructures disposed on each said chip section in said first row;

a plurality of first off-chip electrical contacts disposed at least generally beyond a first end of at least one of said second and third rows;

a plurality of second off-chip electrical contacts disposed at least generally beyond a second end of at least one of said second and third rows; and

a first electrical trace bus located between said second and third rows on each said chip section, wherein said first electrical trace bus comprises a plurality of electrical traces, wherein each said first and second off-chip electrical contact is electrically interconnected with a single electrical path to one of said electrical load-based microstructures by said first electrical trace bus, and wherein said first electrical trace bus on each said chip section is electrically interconnected with at least some of said electrical load-based microstructures in at least one of said second and third rows on the same said chip section.

2. A chip, as claimed in claim 1, wherein:

each of said plurality of chip sections comprises an entire separate die.

3. A chip, as claimed in claim 1, wherein:

each of said plurality of chip sections comprises only part of a separate die.

4. A chip, as claimed in claim 1, further comprising:

a plurality of said first row.

5. A chip, as claimed in claim 4, wherein:

each said first row extends along a first direction, wherein said plurality of said first row collectively span at least one die in a second direction that is perpendicular to said first direction.

6. A chip, as claimed in claim 4, wherein:

each said first row extends along a first direction, wherein said plurality of said first row collectively span a non-integer number of die in a second direction that is perpendicular to said first direction.

7. A chip, as claimed in claim 1, wherein:

each said chip section comprises a mirror array.

8. A chip, as claimed in claim 1, wherein:

each said electrical load-based microstructures comprises an actuator of a mirror assembly, wherein each said mirror assembly comprises a mirror, wherein at least one said actuator is electrically interconnected with each said mirror and further with one said first off-chip electrical contact or one said second off-chip electrical contact.

9. A chip, as claimed in claim 1, wherein:

each of said first and second off-chip electrical contacts is selected from the group consisting of a pad for wire bonding, solder bump bonding, or any combination thereof.

10. A chip, as claimed in claim 1, wherein:

said second and third rows in each said chip section are disposed in at least substantially parallel relation.

11. A chip, as claimed in claim 1, wherein:

said plurality of chip sections comprises first and second said chip sections, wherein at least one said electrical trace extends through each of said first and second said chip sections without being electrically interconnected with any said electrical load-based microstructure in either of said first and second said chip sections.

12. A chip, as claimed in claim 1, wherein:

said first electrical trace bus in each said chip section is electrically interconnected with at least some of said electrical load-based microstructures in only one of said second and third rows.

13. A chip, as claimed in claim 1, wherein:

said first electrical trace bus in each said chip section is electrically interconnected with at least some of said electrical load-based microstructures in both of said second and third rows.

14. A chip, as claimed in claim 1, wherein:

a maximum required number of said electrical traces in any portion of said first electrical trace bus is one-half of a number of said electrical load-based microstructures that are electrically interconnected with said first electrical trace bus.

15. A chip, as claimed in claim 1, wherein:

said first electrical trace bus comprises a plurality of first and second electrical bus sections that are disposed in end-to-end relation, wherein at least one said second electrical bus section is disposed between each adjacent pair of said first electrical bus sections, wherein a number of said electrical traces in each said first electrical bus section is different from a number of said electrical traces in each said second electrical bus section.

16. A chip, comprising:

a plurality of microstructure assemblies;

a plurality of off-chip electrical contacts;

an electrical trace bus comprising a plurality of electrical traces, wherein at least one said electrical trace extends from each of said plurality of off-chip electrical contacts, wherein at least some of said microstructure assemblies are electrically interconnected with said electrical trace bus, wherein said electrical trace bus comprises a plurality of first and second electrical bus sections that are disposed in end-to-end relation and are disposed in alternating relation such that one said second electrical bus section is disposed between each adjacent pair of said first electrical bus sections, wherein each said first electrical bus section has the same number of said electrical traces, wherein each said second electrical bus section has the same number of electrical traces, and wherein the number of said electrical traces in each said first electrical bus section is different from the number of said electrical traces in each said second electrical bus section.

17. A chip, as claimed in claim 16, wherein:

each said microstructure assembly comprises a mirror assembly and at least one actuator, wherein each said actuator is interconnected with said electrical trace bus, wherein each said mirror assembly comprises a mirror.

18. A chip, as claimed in claim 17, wherein:

said electrical trace bus encircles at least some individual said mirrors.

19. A chip, as claimed in claim 16, further comprising:

first and second rows of said plurality of microstructure assemblies, wherein said electrical trace bus is disposed between said first and second rows, wherein said electrical trace bus is electrically interconnected with at least some of said microstructure assemblies in at least one of said first and second rows.

20. A chip, as claimed in claim 19, wherein:

said first and second rows are disposed in at least substantially parallel relation.

21. A chip, as claimed in claim 19, wherein:

said electrical trace bus is electrically interconnected with at least some of said microstructure assemblies in only one of said first and second rows.

22. A chip, as claimed in claim 19, wherein:

said electrical trace bus is electrically interconnected with at least some of said microstructure assemblies in both of said first and second rows.

23. A chip, as claimed in claim 16, wherein:

said plurality of microstructure assemblies are disposed in a single row.

24. A chip, as claimed in claim 16, wherein:

each said microstructure assembly comprises at least one electrical load-based microstructure, wherein a maximum required number of said electrical traces in any portion of said electrical trace bus is one-half of a number of said electrical load-based microstructures assemblies that are electrically interconnected with said electrical trace bus.

25. A chip, comprising:

a plurality of first mirror assemblies, wherein each said first mirror assembly comprises a first mirror;

a plurality of first off-chip electrical contacts; and

a first electrical trace bus electrically interconnected with each of said plurality of first off-chip electrical contacts, electrically interconnected with each of said plurality of first mirror assemblies, and comprising a plurality of electrical traces, wherein said first electrical trace bus individually encircles said first mirror of each of said plurality of first mirror assemblies.

26. A chip, as claimed in claim 25, wherein:

each said first-off chip electrical contact is electrically interconnected with a single electrical path within said first electrical trace bus.

27. A chip, as claimed in claim 25, wherein:

said chip comprises a perimeter region, wherein said plurality of first mirror assemblies are disposed inwardly of said perimeter region, and wherein said plurality of first off-chip electrical contacts are disposed within said perimeter region.

28. A chip, as claimed in claim 25, wherein:

each said first off-chip electrical contact is associated with a specific said first mirror assembly, wherein said first electrical trace bus provides an electrical path between each said first mirror assembly and each of its corresponding said first off-chip electrical contacts.

29. A chip, as claimed in claim 25, wherein:

said first mirror of each of said plurality of first mirror assemblies are alternately disposed on opposite sides of a first reference line.

30. A chip, as claimed in claim 25, further comprising:

a plurality of second mirror assemblies, wherein each said second mirror assembly comprises a second mirror;

a plurality of second off-chip electrical contacts;

a second electrical trace bus electrically interconnected with each of said plurality of second off-chip electrical contacts, electrically interconnected with each of said plurality of second mirror assemblies, and comprising a plurality of electrical traces, wherein said second electrical trace bus individually encircles said second mirror of each of said plurality of second mirror assemblies.

31. A chip, as claimed in claim 30, wherein:

a center of each of said first and second mirrors is disposed on a common reference circle along with a center of other said first and second mirrors.

32. A chip, as claimed in claim 30, wherein:

each said first mirror of said plurality of first mirror assemblies are alternately disposed on opposite sides of a first reference line; and

each said second mirror of said plurality of second mirror assemblies are alternately disposed on opposite sides of a second reference line.

33. A chip, as claimed in claim 32, wherein:

said first and second reference lines are parallel.

34. A chip, as claimed in claim 33, wherein:

a center of each said mirror within said second row is disposed along a second reference line, wherein a center of each said mirror within said third row is disposed along a third reference line, and wherein said second and third reference lines are parallel.

35. A chip, as claimed in claim 33, wherein:

adjacent said mirrors in each of said second and third rows are separated by a common first spacing, wherein said width dimension of each said chip section is the same integer multiple of said first spacing.

36. A chip, as claimed in claim 33, wherein:

a center of each said mirror in said second row is disposed along a reference line with a center of one said mirror in said third row, wherein each said reference line is perpendicular to said second and third rows, and wherein a height dimension of each said chip section is an integer multiple of a common first spacing between said center of mirrors in said second and third rows that are disposed along a common said reference line.

37. A chip, comprising:

a plurality of first mirror assemblies, wherein each said first mirror assembly comprises a first mirror;

a plurality of first off-chip electrical contacts;

a first electrical trace bus electrically interconnected with each of said plurality of first off-chip electrical contacts and comprising a plurality of electrical traces, wherein at least some of said first mirror assemblies are electrically interconnected with said first electrical trace bus, and wherein said first electrical trace bus encircles at least some individual said first mirrors of said plurality of first mirror assemblies;

a plurality of second mirror assemblies, wherein each said second mirror assembly comprises a second mirror;

a plurality of second off-chip electrical contacts; and

a second electrical trace bus electrically interconnected with each of said plurality of second off-chip electrical contacts and comprising a plurality of electrical traces, wherein at least some of said second mirror assemblies are electrically interconnected with said second electrical trace bus, and wherein said second electrical trace bus encircles at least some individual said second mirrors of said plurality of second mirror assemblies.

38. A chip, as claimed in claim 37, wherein:

a center of each of said first and second mirrors is disposed on a common reference circle along with a center of other said first and second mirrors.

39. A chip, as claimed in claim 37, wherein:

each of said plurality of first mirror assemblies is electrically interconnected with said first electrical bus; and

each of said plurality of second mirror assemblies is electrically interconnected with said second electrical bus.

40. A chip, as claimed in claim 37, wherein:

said first electrical trace bus individually encircles each said first mirror of said plurality of first mirror assemblies; and

said second electrical trace bus individually encircles each said second mirror of said plurality of second mirror assemblies.

41. A chip, as claimed in claim 37, wherein:

each said first mirror of said plurality of first mirror assemblies are alternately disposed on opposite sides of a first reference line; and

each said second mirror of said plurality of second mirror assemblies are alternately disposed on opposite sides of a second reference line.

42. A chip, as claimed in claim 41, wherein:

said first and second reference lines are parallel.

43. A chip, as claimed in claim 42, wherein:

a center of each said mirror within said second row is disposed along a second reference line, wherein a center of each said mirror within said third row is disposed along a third reference line, and wherein said second and third reference lines are parallel.

44. A chip, as claimed in claim 42, wherein:

adjacent said mirrors in each of said second and third rows are separated by a common first spacing, wherein said width dimension of each said chip section is the same integer multiple of said first spacing.

45. A chip, as claimed in claim 42, wherein:

a center of each said mirror in said second row is disposed along a reference line with a center of one said mirror in said third row, wherein each said reference line is perpendicular to said second and third rows, and wherein a height dimension of each said chip section is an integer multiple of a common first spacing between said center of mirrors in said second and third rows that are disposed along a common said reference line.