Hydrogen implant for buffer zone of punch-through non EPI IGBT

• US 6,707,111 B2
• Filed: 08/13/2002
• Issued: 03/16/2004
• Est. Priority Date: 05/05/2000
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ng, Chiu, Francis, Richard
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US10/217,988
• Publication Number:
  US 20020190281A1
• Time in Patent Office: 581 Days
• Field of Search: 257/362, 257/E29.027, 257/E29.066, 257/E29.197, 257/E29.201, 257/E21.382
• US Class Current: 257/362
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An IGBT is formed in a thin (less than 250 microns thick) float zone silicon wafer using a hydrogen implant to form an N⁺ buffer layer at the bottom of the wafer. A weak anode is formed on the bottom of the wafer. A single hydrogen implant, or a plurality of hydrogen implants of progressively shallower depth and increasing dose can be used to form the implant in a diffused float zone wafer. The process may also be used to form an N⁺ contact region in silicon to permit a good ohmic contact to the silicon for any type device.

Claims

1. An IGBT comprising an N type wafer of float zone silicon having a thickness of less than about 250 microns;

a DMOS junction pattern and metallizing formed on the top surface of said thin wafer;

an N⁺ buffer zone formed adjacent the bottom surface of said wafer and defined by implanted hydrogen;

a P type weak anode formed on said N⁺ buffer zone and extending to the bottom of said wafer; and

a backside metal contact connected to and across said weak anode.

2. An IGBT device, comprising:

an N type wafer of float zone silicon, the N type wafer having top and bottom surfaces;

a DMOS junction pattern formed on the top surface of the N type wafer;

at least one metal layer arranged on the top surface of the N type wafer;

an N⁺ buffer zone having a top surface and a bottom surface, the N⁺ buffer zone being arranged adjacent to the bottom surface of said N type wafer, the N⁺ buffer zone including implanted hydrogen;

a P type weak anode arranged adjacent to the bottom surface of the N⁺ buffer zone; and

a backside metal contact connected to the P type weak anode.

3. The IGBT device of claim 2, wherein the DMOS junction pattern includes a plurality of spaced P type base regions and a plurality of N type source regions respectively arranged inside the P type base regions.

4. The IGBT device of claim 3, further comprising:

a plurality of gate oxide regions arranged on the top surface of the N type wafer; and

a plurality of conductive polysilicon gate electrodes respectively arranged on the gate oxide regions;

wherein the at least one metal layer forms an electrode, the metal layer being insulated from the conductive polysilicon gate electrodes, the metal layer electrically contacting the P type base regions and the N type source regions.

5. The IGBT device of claim 2, wherein the backside metal contact includes an aluminum layer, a titanium layer arranged adjacent to the aluminum layer, a nickel-vanadium layer arranged adjacent to the titanium layer, and a silver layer arranged adjacent to the nickel-vanadium layer.

6. The IGBT device of claim 2, wherein the N type wafer of float zone silicon has a thickness of less than about 250 microns.

7. The IGBT device of claim 6, wherein the N type wafer of float zone silicon has a thickness of about 80 microns.

8. The IGBT device of claim 6, wherein the N type wafer of float zone silicon has a thickness of about 250 microns.

9. The IGBT device of claim 2, wherein the implanted hydrogen progressively decreases in depth and progressively increases in concentration from the top surface of the N⁺ buffer zone to the bottom surface of the N⁺ buffer zone.